PCF8549USLASH2SLASHF1 datasheet(22/36 Pages) PHILIPS

22 / 36 page

1997 Nov 21

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8549

AC CHARACTERISTICS

Table 8

VDD1 = 1.5 to 6 V; VDD2/2_HV = 2.4 to 5.0 V; VDD2 = VDD2_HV; VSS1 = VSS2 = VSS2_HV = 0 V; VLCD =7to16V;

Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Note

2. Duty cycle of 50 +/-5%.

3. The rise and fall times specified here refer to the driver device (i.e. not PCF8549) and are part of the general fast

I2C-bus specification. When PCF8549 asserts an acknowledge on SDA, the minimum fall time is 10ns. Cb=

capacitive load per bus line.

4. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width < tSW(max).

5. Not tested in production

6. Only for VDD1= 2V to 6V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fOSC

oscillator frequency

kHz

fEXT

external clock frequency

(2)

kHz

tstart

oscillator start up time

(5)

−

450

1600

fFRAME

frame frequency

fEXT = 32 kHz;(1)

−

tVHRL

VDD to RES Low

(5)

1ms

tPWRES

reset low pulse width

400

−−

I2C timing characteristics

fSCLK

SCL clock frequency

(6)

−

400

kHz

tLOW

SCL clock low period

1.3

−−

tHIGH

SCL clock high period

0.6

−−

tSU;Data

Data set-up time

100

−−

tHD;Data

Data hold time

−

0.9

SCL and SDA rise time

(3)

20 + 0.1 Cb

−

300

SCL and SDA fall time

(3)

20 + 0.1 Cb

−

300

Capacitive load represented by each

bus line

−−

400

tSU;STA

setup time for a repeated START con-

dition

0.6

−−

tHD;STA

start condition hold time

0.6

−−

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold-time

−−

tSU;STO

setup time for STOP condition

0.6

−−

tSW

tolerable spike width on bus

(4)

−−

tBUF

BUS free time between a STOP and

START condition

1.3

−−

FRAME

EXT

520

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