Page 16

ams Datasheet

Document Feedback

[v1-00] 2016-Apr-12

TSL2568, TSL2569 − Principles of Operation

Analog-to-Digital Converter

The TSL256x contains two integrating analog-to-digital

converters (ADC) that integrate the currents from the channel

0 and channel 1 photodiodes. Integration of both channels

occurs simultaneously, and upon completion of the conversion

cycle the conversion result is transferred to the channel 0 and

channel 1 data registers, respectively. The transfers are double

buffered to ensure that invalid data is not read during the

transfer. After the transfer, the device automatically begins the

next integration cycle.

Digital Interface

Interface and control of the TSL256x is accomplished through

a two-wire serial interface to a set of registers that provide

access to device control functions and output data. The serial

interface is compatible with System Management Bus (SMBus)

versions 1.1 and 2.0, and I²C bus Fast-Mode. The TSL256x offers

three slave addresses that are selectable via an external pin

(ADDR SEL). The slave address options are shown in Figure 17.

Figure 17:

Slave Address Selection

Note(s):

1. The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I²C protocols (see SMBus and I²C Protocols). A read/write

bit should be appended to the slave address by the master device to properly communicate with the TSL256X device.

ADDR SEL Terminal Level

Slave Address

SMB Alert Address

GND

0101001

0001100

Float

0111001

0001100

VDD

1001001

0001100

Principles of Operation