ams Datasheet

Page 23

[v1-00] 2016-Apr-12

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TSL2568, TSL2569 − Principles of Operation

Command Register

The Command Register specifies the address of the target

register for subsequent read and write operations. The Send

Byte protocol is used to configure the Command Register. The

Command Register contains eight bits as described in

Figure 28. The Command Register defaults to 00h at power on.

Figure 28:

Command Register

Note(s):

1. An I²C block transaction will continue until the Master sends a stop condition. See Figure 25 and Figure 26. Unlike the I²C protocol,

the SMBus read/write protocol requires a Byte Count. All four ADC Channel Data Registers (Ch through Fh) can be read simultaneously

in a single SMBus transaction. This is the only 32-bit data block supported by the TSL2568 SMBus protocol. The BLOCK bit must be

set to 1, and a read condition should be initiated with a COMMAND CODE of 9Bh. By using a COMMAND CODE of 9Bh during an

SMBus Block Read Protocol, the TSL2568 device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated

in Figure 26. A write condition should not be used in conjunction with the Bh register.

7

6

5432

10

CMD

CLEAR

WORD

BLOCK

ADDRESS

Field

Bit

Description

CMD

7

Select Command Register. Must write as 1.

CLEAR

6

Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is

self clearing.

WORD

5

SMB Write/Read Word Protocol. 1 indicates that this SMB transaction is using either

the SMB Write Word or Read Word protocol.

BLOCK

4

Block Write/Read Protocol. 1 indicates that this transaction is using either the Block

Write or the Block Read protocol. (1)

ADDRESS

3:0

Register Address. This field selects the specific control or status register for

following write and read commands according to Figure 27.