AD9957SLASHPCBZ datasheet(33/60 Pages) AD

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AD9957

Rev. 0 | Page 33 of 60

CLOCK INPUT (REF_CLK)

REFCLK OVERVIEW

The AD9957 supports a number of options for producing the

internal SYSCLK signal (that is, the DAC sample clock) via the

REF_CLK input pins. The REF_CLK input can be driven

directly from a differential or single-ended source, or it can

accept a crystal connected across the two input pins. There is

also an internal phase-locked loop (PLL) multiplier that can be

independently enabled. A block diagram of the REF_CLK

functionality is shown in Figure 47. The various input configu-

rations are controlled by means of the XTAL_SEL pin and

control bits in the CFR3 register. Figure 47 also shows how the

CFR3 control bits are associated with specific functional blocks.

REF_CLK

PLL

VCO

SELECT

DIVIDE

CHARGE

PUMP

OUT

PLL_LOOP_FILTER

ENABLE

PLL_LOOP_FILTER

DRV

CFR3

<31:30>

REFCLK_OUT

XTAL_SEL

REFCLK

INPUT

SELECT

LOGIC

SYSCLK

ICP

CFR3

<21:19>

CFR3

<7:1>

VCO

CFR3

<26:24>

÷2

INPUT DIVIDER BYPASS

CFR3<15>

PLL_ENABLE

CFR3

<8>

INPUT DIVIDER

RESET

CFR3<14>

Figure 47. REF_CLK Block Diagram

The PLL enable bit is used to choose between the PLL path or

the direct input path. When the direct input path is selected, the

REF_CLK pins must be driven by an external signal source

(single-ended or differential). Input frequencies up to 2 GHz are

supported. For input frequencies greater than 1 GHz, the input

divider must be enabled for proper operation of the device.

When the PLL is enabled, a buffered clock signal is available at

the REFCLK_OUT pin. This clock signal is the same frequency

as the REF_CLK input. This is especially useful when a crystal

is connected, because it gives the user a replica of the crystal

clock for driving other external devices. The REFCLK_OUT

buffer is controlled by two bits as listed in Table 7.

Table 7. REFCLK_OUT Buffer Control

CFR3<31:30>

REFCLK_OUT Buffer

Disabled

Low output current

Medium output current

High output current

CRYSTAL DRIVEN REF_CLK

When using a crystal at the REF_CLK input, the resonant

frequency should be approximately 25 MHz. Figure 48 shows

the recommended circuit configuration.

REF_CLK

39pF

XTAL

Figure 48. Crystal Connection Diagram

DIRECT DRIVEN REF_CLK

When driving the REF_CLK inputs directly from a signal

source, either single-ended or differential signals can be used.

With a differential signal source, the REF_CLK pins are driven

with complementary signals and ac-coupled with 0.1 μF

capacitors. With a single-ended signal source, either a single-

ended-to-differential conversion can be employed or the

REF_CLK input can be driven single-ended directly. In either

case, 0.1 μF capacitors are used to ac couple both REF_CLK

pins to avoid disturbing the internal dc bias voltage of ~1.35 V.

See Figure 49 for more details.

The REF_CLK input resistance is ~2.5 kΩ differential (~1.2 kΩ

single-ended). Most signal sources have relatively low output

impedances. The REF_CLK input resistance is relatively high,

therefore, its effect on the termination impedance is negligible

and can usually be chosen to be the same as the output imped-

ance of the signal source. The bottom two examples in Figure 49

assume a signal source with a 50 Ω output impedance.

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