AD9957SLASHPCBZ datasheet(9/60 Pages) AD

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AD9957

Rev. 0 | Page 9 of 60

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

I/O1

Description

1, 24, 61, 72, 86,

87, 93, 97 to 100

Not Connected. Allow device pin to float.

PLL_LOOP_FILTER

PLL-Loop Filter Compensation. See External PLL Loop Filter Components section.

3, 6, 89, 92

AVDD (1.8V)

Analog Core VDD. 1.8 V analog supplies.

74 to 77, 83

AVDD (3.3V)

Analog DAC VDD. 3.3 V analog supplies.

17, 23, 30, 47, 57,

DVDD (1.8V)

Digital Core VDD. 1.8 V digital supplies.

11, 15, 21, 28, 45,

56, 66

DVDD_I/O (3.3V)

Digital Input/Output VDD. 3.3 V digital supplies.

4, 5, 73, 78, 79, 82,

85, 88, 96

AGND

Analog Ground.

13, 16, 22, 29, 46,

58, 62, 63, 65

DGND

Digital Ground.

SYNC_IN+

Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from

external master to synchronize internal subclocks. See the Synchronization of Multiple

Devices section.

SYNC_IN−

Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from

external master to synchronize internal subclocks. See the Synchronization of Multiple

Devices section.

SYNC_OUT+

Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from

internal device subclocks to synchronize external slave devices. See the Synchronization

of Multiple Devices section.

SYNC_OUT−

Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from

internal device subclocks to synchronize external slave devices. See the Synchronization

of Multiple Devices section.

SYNC_SMP_ERR

Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates

that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−. See the

Synchronization of Multiple Devices section.

MASTER_RESET

Master Reset, Digital Input (Active High). This pin clears all memory elements and sets

registers to default values.

EXT_PWR_DWN

External Power-Down, Digital Input (Active High). A high level on this pin initiates the

currently programmed power-down mode. See the Power-Down section of this

document for further details. If unused, tie to ground.

PLL_LOCK

PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock

multiplier PLL has acquired lock to the reference clock input.

CCI_OVFL

CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow.

This pin remains high until the CCI overflow condition is cleared.

25 to 27, 31 to 39,

42 to 44, 48 to 50

D<17:0>

Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I

and Q vectors for the modulator to upconvert.

SPORT I-DATA

In Blackfin interface mode, this pin serves as the I-data serial input.

SPORT Q-DATA

In Blackfin interface mode, this pin serves as the Q-data serial input.

PDCLK/TSCLK

Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details.

TxENABLE

Transmit Enable, Digital Input (Active High). See the Signal Processing section for details.

FS Input. In Blackfin interface mode, this pin serves as the FS input to receive the RFS

output signal from the Blackfin.

RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude

scaling function. When this function is engaged, a high sweeps the amplitude from the

beginning RAM address to the end. A low sweeps the amplitude from the end RAM

address to the beginning. If unused, connect to ground or supply.

52 to 54

PROFILE<2:0>

Profile Select Pins, Digital Inputs (Active High). These pins select one of eight

phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state

of one of these pins transfers the current contents of all I/O buffers to the corresponding

registers. State changes should be set up to the SYNC_CLK pin.

SYNC_CLK

Output System Clock/4, Digital Output (Clock). The I/O_UPDATE and PROFILE<2:0> pins

should be set up to the rising edge of this signal.

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