AD9957SLASHPCBZ datasheet(24/60 Pages) AD

24 / 60 page

AD9957

Rev. 0 | Page 24 of 60

The modulation is performed digitally avoiding the phase

offset, gain imbalance, and crosstalk issues commonly

associated with analog modulators. Note that the modulated,

so-called signal is a number stream sampled at the rate of

SYSCLK, the same rate at which the DAC is clocked.

The orientation of the modulated signal with respect to the

carrier is controlled by a spectral invert bit. This bit resides in

each of the four profile registers. By default, the time domain

output of the quadrature modulator takes the form

I(t) × cos(ωt) − Q(t) × sin(ωt)

(2)

When the spectral invert bit is asserted, it becomes

I(t) × cos(ωt) + Q(t) × sin(ωt)

(3)

DDS CORE

The direct digital synthesizer (DDS) block generates sine

and/or cosine signals. In single tone mode, the DDS generates

either a digital sine or cosine waveform based on the select DDS

sine output bit. In QDUC mode, the DDS generates the quadra-

ture carrier reference signal that digitally modulates the I/Q

baseband signal.

The DDS output frequency is tuned using registers accessed via

the serial I/O port. This allows for both precise tuning and

instantaneous changing of the carrier frequency.

The equation relating output frequency (fOUT) of the DDS to the

frequency tuning word (FTW) and the system clock (fSYSCLK) is

SYSCLK

OUT

FTW

⎟

⎠

⎞

⎜

⎝

⎛

(4)

where FTW is a decimal number from 0 to 2,147,483,647 (231 − 1).

Solving for FTW yields

⎟

⎠

⎞

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

SYSCLK

OUT

round

FTW

(5)

where the round() function means to round the result to the

nearest integer. For example, for fOUT = 41 MHz and fSYSCLK =

122.88 MHz, then FTW = 1,433,053,867 (0x556AAAAB).

In single tone mode, the DDS frequency, phase, and amplitude

are all programmable via the serial I/O port. The amplitude is

controlled by means of a digital multiplier using a 14-bit

fractional scale value called the amplitude scale factor (ASF).

The LSB weight is 2−14, yielding a multiplier range of 0 to

0.99993896484375 (1 − 2−14). The phase offset is controlled by

means of a digital adder that uses a 14-bit offset value called the

phase offset word (POW). The adder is situated between the

phase accumulator and the angle-to-amplitude conversion logic

in the DDS core. The adder applies the POW to the instantaneous

phase values produced by the DDS phase accumulator. The

adder is MSB-aligned with the phase accumulator yielding an

LSB weight of 2−14 (which equates to a resolution of ~0.022° or

~0.000383 radians). Both the ASF and the POW are available

for each of the eight profiles.

INVERSE SINC FILTER

The sampled carrier data stream is the input to the on board

digital-to-analog converter. The DAC output spectrum is

shaped by the characteristic sin(x)/x (or sinc) envelope, due to

the intrinsic zero-order hold effect associated with DAC-

generated signals. The shape of the sinc envelope is well known

and can be compensated for. This compensation is provided by

the inverse sinc filter preceding the DAC.

The inverse sinc filter is implemented as a digital FIR filter. Its

response characteristic very nearly matches the inverse of the

sinc envelope, as shown in Figure 37 (along with the sinc

envelope for comparison).

The inverse sinc filter is enabled through a bit in the register

map. The filter tap coefficients are listed in Table 5. The filter

predistorts the data prior to its arrival at the DAC to compensate

for the sinc envelope that otherwise distorts the spectrum.

When the inverse sinc filter is enabled, it introduces an ~3.0 dB

insertion loss. The inverse sinc compensation is effective for

output frequencies up to 40% (nominally) of the DAC sample rate.

Table 5. Inverse Sinc Filter Tap Coefficients

Tap No.

Tap Value

Tap No.

−35

+134

−562

+6729

In Figure 37, it can be seen that the sinc envelope introduces a

frequency dependent attenuation that can be as much as 4 dB at

the Nyquist frequency (half of the DAC sample rate). Without

the inverse sinc filter, the DAC output also suffers from the

frequency dependent droop of the sinc envelope. The inverse

sinc filter effectively flattens the droop to within ±0.05 dB as

shown in Figure 38, which shows the corrected sinc response

with the inverse sinc filter enabled.

–1

–2

–3

–4

0.1

0.2

0.4

0.3

0.5

FREQUENCY RELATIVE TO DAC SAMPLE RATE

INVERSE

SINC

Figure 37. Sinc and Inverse Sinc Responses

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