AD9957SLASHPCBZ datasheet(44/60 Pages) AD

44 / 60 page

AD9957

Rev. 0 | Page 44 of 60

Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is

the LSB for that register.

Table 13. Control Registers

Name

(Serial

Address)

Bit

Range

(Internal

Address)

Bit 7

(MSB)

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

<31:24>

RAM

Enable

Open

RAM

Playback

Destination

Open

Operating Mode

0x00

<23:16>

Manual

OSK

External

Control

Inverse

Sinc Filter

Enable

Clear CCI

Open

Select

DDS

Sine

Output

0x00

<15:8>

Open

Autoclear

Phase

Accum

Open

Clear Phase

Accum

Load ARR @

I/O Update

OSK

Enable

Select

Auto-

OSK

0x00

Control

Function

CFR1

(0x00)

<7:0>

Digital

Power-

Down

DAC Power-

Down

REFCLK

Input

Power-Down

Aux DAC

Power-Down

External

Power-Down

Control

Auto

Power-Down

Enable

SDIO

Input

Only

LSB First

0x00

<31:24>

Blackfin

Interface

Mode

Active

Blackfin Bit

Order

Blackfin

Early Frame

Sync Enable

Open

0x00

<23:16>

Internal

I/O Update

Active

SYNC_CLK

Enable

Open

Read

Effective

FTW

0x40

<15:8>

I/O Update Rate Control

PDCLK Rate

Control

Data Format

PDCLK

Enable

PDCLK

Invert

TxEnable

Invert

Q-First

Data

Pairing

0x08

Control

Function

CFR2

(0x01)

<7:0>

Matched

Latency

Enable

Data

Assembler

Hold Last

Value

Sync Timing

Validation

Disable

Open

0x20

<31:24>

DRV0<1:0>

Open

VCO SEL<2:0>

0x1F

<23:16>

Open

ICP<2:0>

Open

0x3F

<15:8>

REFCLK

Input

Divider

Bypass

REFCLK

Input

Divider

ResetB

Open

PLL

Enable

0x40

Control

Function

CFR3

(0x02)

<7:0>

N<6:0>

Open

0x00

<31:24>

Open

0x00

<23:16>

Open

0x00

<15:8>

Open

0x7F

Auxiliary

DAC

Control

(0x03)

<7:0>

FSC<7:0>

0x7F

<31:24>

I/O Update Rate<31:24>

0xFF

<23:16>

I/O Update Rate<23:16>

0xFF

<15:8>

I/O Update Rate<15:8>

0xFF

I/O Update

Rate

(0x04)

<7:0>

I/O Update Rate<7:0>

0xFF

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