DATA SHEET

SE4150L: GPS Receiver IC

Preliminary Datasheet

Skyworks Solutions, Inc.

• Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

202445B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 1, 2019

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connected directly to MIX_IN (pin 11) in some

applications.

The image reject mixer ensures that the receiver’s full

sensitivity is achieved without an external filter. For

applications where additional selectivity is required,

an external filter can be added between the

ANT_SW_OUT (pin 7) and MIX_IN (pin 11) pins.

IF Filter

The SE4150L includes a fully integrated Intermediate

Frequency (IF) filter which provides excellent

interference rejection with no additional external

components. The filter has a 3rd order Butterworth

bandpass response.

The bandpass response has a nominal bandwidth of

2.2 MHz; the nominal center frequency is preset to

4.092 MHz. These parameters ensure very low

implementation

loss

in

all

frequency

plan

configurations.

AGC and ADC

The SE4150L features a linear IF chain with 2-bit

SIGN / MAG ADC. SIGN output is pin 20, and MAG

output is pin 19.

An Automatic Gain Control (AGC) system is included.

This provides 50 dB of gain control range so that the

output signal level is held at an optimum level at the

input of the ADC.

The MAG data controls the AGC loop, such that the

MAG bit is active (HIGH) for approximately 33% of the

time.

The SIGN (pin 20) and MAG (pin 19) signals are

latched by the falling edge of the sample clock,

CLK_OUT (pin 21) within the ADC. The SIGN and

MAG signals, once they arrive at the GPS baseband

IC, are best re-sampled on the rising edge of

CLK_OUT, for optimum sample and hold.

The AGC time constant is determined by a single

external capacitor, connected between VAGC (pin 1),

and VSSN / GND. The settling-time of the AGC is

within 10ms with a 10nF capacitor.

PLL and Loop Filter

The entire Phase-Locked Loop (PLL) generating the

local oscillator for the mixer is contained on-chip.

A classic three-element RC PLL loop filter has been

implemented on-chip between the output of the

internal charge pump and GND / VSSN. The PLL

follows a classic 3rd-order response. Typical PLL

Loop- Bandwidth is set to be approx. 200kHz.

The reference frequency for the PLL is provided by an

external reference source; normally a TCXO.

TCXO Connection

The SE4150L can be used with an external TCXO.

The TCXO should have a clipped sinewave signal

output which is connected to the TCXO_IN (pin 15)

input.

The supply to the external TCXO can be connected to

pin 13 of the SE4150L. The VCC_TCXO supply is

disabled when the SE4150L is in stand-by mode.

The VCC_TCXO pin can be left floating if a direct

connection from VCC to the power supply of the

external TCXO is desired.

VCC_TCXO supply modes

RX_EN

Logic

level

CLK_EN

Logic

level

Note

VCC_TCXO

output

‘0’

‘0’

-

OPEN

‘0’

‘1’

1

VCC

‘1’

‘1’

1

VCC

Note:

(1) TCXO supply current limited to 30 mA

max.

Clock and Data Output Coupling

The high input sensitivity achieved by the SE4150L’s

internal LNA requires careful control of harmonically

related sources of interference.

For this reason the CLK_OUT (pin 21), SIGN (pin 20)

and MAG (pin 19) outputs provide carefully controlled

current and slew-rate. The data and clock outputs of

the SE4150L are specified to drive up to 15pF load

(N.B. the max standard CMOS input capacitance is

10pF). The output drive of the SE4150L can be

adjusted with a resistor connected between VDDQ

(pin 14) and RVI (pin 12), as shown in the Logic

Output Current Drive Adjustment Settings section

below.

The output current drive is determined by a bias

current ratio internal to the SE4150L and the external

resistor.