DATA SHEET

SE4150L: GPS Receiver IC

Preliminary Datasheet

Skyworks Solutions, Inc.

• Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

202445B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 1, 2019

15

Logic Level Characteristics – ANT_DET (pin 8) only

Conditions: VCC = VDDN = 3.3 V, TA = 25°C

Symbol

Parameter

Note

Min.

Typ.

Max.

Unit

VIH_ADET

Logic High (HI) Input Voltage

1

0.7 VDDN

-

VDDN

V

VIL_ADET

Logic Low (LO) Input Voltage

1

0

-

0.4

V

IIH_ADET

Input Current – Logic HI input voltage

1

-

-150

-

μA

IIL_ADET

Input Current – Logic LO input

voltage

1

-

(VDDN-VIL_ADET)

/0.1

-

μA

CILOAD_ADET

Input Load Capacitance

1

-

-

TBD

pF

VOH_ADET

Logic High (HI) Output Voltage

2

VDDN - 0.1V

-

VDDN

V

VOL_ADET

Logic Low (LO) Output Voltage

2

0

-

0.1

V

IOH_ADET

Output Current - Logic HI Output

Voltage

2, 3

-

(VDDN-VOH_ADET)

/0.05

-

μA

IOL_ADET

Output Current - Logic LO Output

Voltage

2, 3

-

-300

-

μA

COLOAD

Output Load Capacitance

2

-

-

15

pF

Note:

(1)

When ANT_DET (pin 8) forced with an external logic input.

(2)

When ANT_DET (pin 8) used as a logic output.

(3)

The ANT_DET (pin 8) output drive is asymmetric. When outputting logic ‘0’, the output looks like a

current sink of 300uA. When outputting logic ‘1’, the output looks like a pull up resistor of 50kohm to

VCC. The 300uA sink is enough to pull the output logic level to GND, with a 10kΩ resistor to VCC.

Logic Output Current Drive Adjustment Settings

The Logic Outputs on the SE4150L can be adjusted to compensate for parasitics in application board layout. This can

be achieved by adding a resistor between RVI (pin 12) and VDDQ (pin 14) as shown below.

The additional interface capacitance of PCB tracking and connectors between the SE4150L output and baseband IC

input is included in these figures.

These figures are Typical only, and are not guaranteed across temperature and silicon process.

Conditions:

VCC = VDDN = 3.3 V, TA = 25°C

Current Setting Resistor Value

(RVI (pin 12) to VDDQ (pin 14))

(Ω)

Maximum Allowable

Capacitive Loading

(pF)

Current Drive

Level

Not Fitted

7.5

Nominal

100K

9

X 1.2

39K

10.5

X 1.4

0R

15

X 2.0