DATA SHEET

SE4150L: GPS Receiver IC

Preliminary Datasheet

Skyworks Solutions, Inc.

• Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

202445B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 1, 2019

14

Logic Level Characteristics – Input Pins

Conditions: VCC = VDDN = 3.3 V, TA = 25°C. Applies to logic pins used as inputs: RX_EN (pin 5), HW_0 (pin 16),

HW_1 (pin 17) and CLK_EN (pin 18).

Symbol

Parameter

Note

Min.

Typ.

Max.

Unit

VIH

Logic High Input Voltage

-

0.7 VDDN

-

VDDN

V

VIL

Logic Low Input Voltage

-

0

-

0.4

V

IIH

Input Current Logic High Voltage

-

-

200

-

nA

IIH_RX_EN

Input Current Logic High Voltage for

RX_EN Input (pin 5)

1

-

16.5

-

μA

IIL

Input Current Logic Low Voltage

-

-

-200

-

nA

CILOAD

Input Load Capacitance

-

-

-

2

pF

Note:

(1)

Applies to RX_EN (pin 5) only. Figure dominated by 200kΩ (nom) on-chip pull-down resistor.

Logic Level Characteristics – Output Pins

Conditions: VCC = VDDN = 3.3 V, TA = 25°C. Applies to logic pins used as outputs: CLK_OUT (pin 21), SIGN (pin 20),

and MAG (pin 19).

Symbol

Parameter

Note

Min.

Typ.

Max.

Unit

VOH

Logic High Output Voltage

-

VDDN - 0.1V

-

VDDN

V

VOL

Logic Low Output Voltage

-

0

-

0.1

V

COLOAD

Output Load Capacitance

-

-

-

15

pF

Note:

(1)

Output Current set at Nominal level; no Current Setting Resistor on RVI (pin 12). Positive value

indicates current source; negative value indicates current sink.

ANT_DET (pin 8) Characteristics

ANT_DET (pin 8) is an input and output logic signal. In output mode, it operates as an indicator of the current through

ANT_BIAS (pin 2). In input mode, an input needs to be applied which overrides the output from the pin, to force the

internal antenna-switch.

ANT _BIAS

Current

Note

External Forced I/P on

ANT_DET

Isink

Impedance

to VCC

ANT_DET Output

Logic Level

Antenna Switch

Signal Path (to

ANT_SW_OUT)

<0.85mA

1

-

300 uA

∞

LO (0)

LNA_IN

>1mA

2

-

0 uA

50kΩ

HI (1)

ANT1_IN

<0.85mA

1,3

Low impedance to VCC

150 uA

∞

Forced HI

ANT1_IN

>1mA

2

Low impedance to GND

0 uA

100kΩ

Forced LO

LNA_IN

Note:

(1)

No external active antenna connected.

(2)

External active antenna connected

(3)

The difference between the internal logic level and the output level is sensed and the output drive is

reduced, to save current