DATA SHEET

SE4150L: GPS Receiver IC

Preliminary Datasheet

Skyworks Solutions, Inc.

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7

Hardware Configuration

The SE4150L can be configured to change the LNA

Gain/Linearity and the Mixer Gain/Linearity by means

of the settings on the HW_0 (pin 16) and HW_1

(pin 17) logic inputs. The adjustment of the gain and

linearity allow the SE4150L to be used in differing

environments, either with significant co-located

interference sources (e.g. mobile phone) or no

interference sources (e.g. PND).

LNA Gain & Linearity Selection

The SE4150L supports two settings for gain and input

IP3 in the on-chip LNA.

Supported LNA Gain & Linearity Modes

LNA

Mode

LNA

Gain

LNA IIP3

Hi Gain

20 dB

-6 dBm

Lo Gain

17 dB

-12 dBm

Mixer Gain Selection

The SE4150L supports two gain settings for the on-

chip mixer.

Supported Mixer Gain Modes

Mixer

Mode

Mixer

Buffer

Gain

Hi Gain

32 dB

Lo Gain

24 dB

The following truth table gives the settings for

hardware configuration of both the LNA Gain/Linearity

and also the Mixer Gain/Linearity.

Hardware Configuration

LNA Mode

Mixer Mode

Selection value

(HW_<1:0>)

Hi Gain

Hi Gain

11

Lo Gain

Lo Gain

00

Power Management

The SE4150L uses RX_EN (pin 5) to put the device

into standby. In standby mode, all circuits are off and

the device consumes only leakage current.

The RX_EN input has a 200 kΩ pull-down resistor to

GND, on-chip. This ensures that the RFIC will put

itself in standby when the RX_EN controller on the

baseband is tri-stated to an impedance much greater

than 200 kΩ.

The internal LNA can be disabled by connecting the

Vcc supply connection to the LNA, VCC_LNA (pin 6)

to GND. This may be desirable in some applications,

and prevents the LNA from consuming any current,

saving approximately 5mA.

The sample clock output, CLK_OUT (pin 21) can be

kept active by setting CLK_EN (pin 18) pin to logic ‘1’

(HI). This will cause all circuits required to produce

the CLK_OUT signal to remain active, even when the

receiver is forced into Standby mode (RX_EN (pin 5)

set to Logic ‘0’).

Logic Interfacing

The SE4150L Logic Inputs can either be driven from

an external baseband IC, or permanently set by

connecting to either VDDN (pin 22) for Logic ‘1’, or

GND for Logic ‘0’. The digital interface on the

SE4150L, supplied from VDDN, has been designed to

operate at the same voltage as the GPS baseband

IC.

The ANT_DET (pin 8) output is sourced from the

antenna current detector, and is also connected to the

internal antenna switch; the switch toggles the RF

signal source automatically when an external active

antenna is connected.

The antenna current detector can be overridden by

applying a low impedance source (<10kΩ impedance)

at VDDN (pin 22) or GND levels to ANT_DET (pin 8),

such as a logic output from a GPIO pin on the GPS

Baseband IC. This means that automatic switching

can be activated by leaving the GPIO pin on the

Baseband IC in a high impedance state, or overridden

by setting to the appropriate state.

The SE4150L Logic Input and Output signals are

shown in the following tables: