MPC826XACVR datasheet(3/52 Pages) FREESCALE

3 / 52 page

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

Features

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without

inlining and 1.90 Dhrystones MIPS/MHz with

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

•

Separate power supply for internal logic and for I/O

•

Separate PLLs for G2 core and for the CPM

— G2 core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

•

64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

•

32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

•

60x-to-PCI bridge (MPC8265 and MPC8266 only)

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

•

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

•

Twelve-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-

definable peripherals

— Byte write enables and selectable parity generation

MPC826XACVR 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

MPC826XACVR 数据表(HTML) 3 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表下载