MPC8541ECVTAPE datasheet(47/84 Pages) FREESCALE

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

JTAG

Figure 30 provides the AC test load for TDO and the boundary-scan outputs of the MPC8541E.

Figure 30. AC Test Load for the JTAG Interface

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in

question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see

Figure 30). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH

symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the

tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to

the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that,

in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design.

Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol 2

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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