MPC8541ECVTAPE datasheet(49/84 Pages) FREESCALE

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

I2C

Figure 34 provides the test access port timing diagram.

Figure 34. Test Access Port Timing Diagram

12 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8541E.

12.1

I2C DC Electrical Characteristics

Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8541E.

Table 39. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

VIH

0.7

× OV

OVDD+ 0.3

Input low voltage level

VIL

–0.3

0.3

× OV

Low level output voltage

VOL

00.2

× OV

Output fall time from VIH(min) to VIL(max) with a bus

capacitance from 10 to 400 pF

tI2KLKV

20 + 0.1

× C

250

Pulse width of spikes which must be suppressed by the

input filter

tI2KHKL

050

Input current each I/O pin (input voltage is between 0.1

OVDD and 0.9 × OVDD(max)

–10

μA4

Capacitance for each I/O pin

—10

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. CB = capacitance of one bus line in pF.

3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the

digital filter used.

4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

VM = Midpoint Voltage (OVDD/2)

tJTIVKH

tJTIXKH

JTAG

External Clock

Output Data Valid

tJTKLOX

tJTKLOZ

tJTKLOV

Input

Data Valid

Output Data Valid

TDI, TMS

TDO

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