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MPC8541ECVTAPE 数据表(PDF) 18 Page - Freescale Semiconductor, Inc

部件名 MPC8541ECVTAPE
功能描述  PowerQUICC??III Integrated Communications Processor Hardware Specifications
PDF  84 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8541ECVTAPE 数据表(HTML) 18 Page - Freescale Semiconductor, Inc

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
DDR SDRAM
Figure 3 shows the DDR SDRAM output timing for address skew with respect to any MCK.
Figure 3. Timing Diagram for tAOSKEW Measurement
Figure 4 shows the DDR SDRAM output timing diagram for the source synchronous mode.
Figure 4. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
ADDR/CMD
MCK[n]
MCK[n]
tMCK
tAOSKEWmax)
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
ADDR/CMD
tDDKHAS ,tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX ,tDDKHCX
Write A0
NOOP
tDDKLME
tDDKHMP



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