Philips Semiconductors

Objective specification

SA9024

900 MHz transmit modulator and 1.3 GHz

fractional–N synthesizer

1997 Aug 01

12

Table 1. Function Table

Symbol

Bits

Function

FMOD

1

Fractional-N modulus selection flag:

‘0’ = modulo 8

‘1’ = modulo 5

NF

3

Fractional-N increment

NMAIN

16

Main divider ratio; 512 to 65,535 allowed

NREF

10

Reference divider ratio; 4 to 1,023 allowed,

RSM, RSA = “0 0”

RSM

2

Reference select for main phase detector

RSA

2

Reference select for auxiliary phase detector

FDAC

8

Fractional compensation charge pump current

DAC

NAUX

14

Auxiliary divider ratio; 128 to 16,384 allowed

CP

2

Charge pump current ratio select (see table 1)

LD

2

Lock detect output select (see table 2)

PD1

1

PD1 = 0 for power down; shuts off power to

main divider and main chargepumps, anded

with PD2 to turn off ref. divider.

PD2

1

PD2 = 0 for power down; shuts off power to

auxiliary divider, and auxiliary charge pumps;

anded with PD1 to turn off ref. divider.

PC

8

Power control (see note 3)

M

2

÷M, M = 6, 7, 8, 9 (see note 4)

SE

1

Transmit offset synthesizer on/off

TM

1

Transmit mode: ‘0’ = DUAL

AD

1

Mode control, 1 = digital; 0 = analog

SM1

1

Sleep mode 1

SM2

1

Sleep mode 2

1. Data bits are shifted in on the the leading clock edge, with the

least significant bit (LSB) first and the most significant bit (MSB)

last.

2. On the rising edge of the strobe and with the address decoder

output = 1, the contents of the input shift register are transferred

to the working registers. The strobe rising edge comes one half

clock period after the clock edge on which the MSB of a word is

shifted in.

3. The PC bits are used for the power control function. Eight (8)

bits of data allows for appropriate resolution of the power control.

00000000 = 0 dB: 11111111 = –45.9 dB (= 255

 0.18).

4. The M bits are used to program the

÷M counter for integer values

between 6 and 9. 00 = 6, 01 = 7, 10 = 8, 11 = 9.

5. The TM bit is used to put the SA9024 into DUAL mode operation.

In DUAL mode (TM = 0).

6. The AD bit allows a reduction in the linearity of the DUAL output

driver while in AMPS mode.

buffers on; SM1 = 0, buffers off.

8. The SM2 bit is used to shut down the RCLK buffer. SM2 = 1,

buffer on; SM2 = 0, buffer off.

9. The SE bit turns on and off the offset loop synthesizer circuits.

SE = 1, synthesizer on; SE = 0, synthesizer off.

10. The LOCK bits determine what signal is present on the LOCK

pin as follows:

Table 2.

Lock Detect Output Select*

LOCK

LOCK Pin Function

00

Main, auxiliary and offset lock condition

01

Main and auxiliary lock condition

10

Main lock detect condition

11

Auxiliary lock condition

*When a section is in power down mode, the lock indicator for that

section is high.