Philips Semiconductors

Objective specification

SA9024

900 MHz transmit modulator and 1.3 GHz

fractional–N synthesizer

1997 Aug 01

21

A lock detect signal is provided and ANDed together with lock detect

signals from both the main channel synthesizer and auxiliary

synthesizer. While in standby mode, the lock detect signal will be

forced to a valid lock state so that the lock detect signal will indicate

when the main and auxiliary phase detectors have achieved phase

lock.

Divide by M

The

÷M is a 2-bit programmable divider which can be configured for

ney integer divide from 6 to 9. The divider is used to convert the

VCO output down to the reference frequency before feeding it into

the phase comparator.

VCO

This oscillator is used to generate the transmit IF frequency between

90MHz and 180MHz. The VCO tank is configured using a parallel

inductor tuning varactor diode. DC blocking capacitors are used to

isolate the varactor control voltage from the VCO tank DC bias

voltages.

and the VCO output. The Single Sideband Up-converter (SSB) is

an active Gilbert cell multiplier (matched pair), combined with two

quadrature phase shift networks and a low pass filter. The SSB

up-converter is used to reject the unwanted upper sideband that

would normally occur during the up-conversion process.

I/Q Modulator

The quadrature modulator is an active Gilbert cell multiplier

(matched pair) with cross coupled outputs. These outputs are then

provided to the variable gain amplifier. When the in-phase input I =

cos (

ωt) and the quadrature-phase input Q = sin (ωt) (i.e., Q lags I

by 90

°), the resulting output should be upper single sideband.

Variable Gain Amplifiers

The variable gain amplifiers are used to control the output level of

the device, with a power control range of 45.9dB. The output stages

are differential, matched from 200

Ω to 50Ω.

Power Control

The power control range should be greater than or equal to 45.9dB,

having a monotonically decreasing slope, with 0dB = +11.5 dBm

nominal. Eight bits are available for power control programming.

The top 6 bits (PC7 to PC2) provide coarse attenuation with .6dB

step size accuracy. The bottom 2 bits provide fine attenuation with

.18 dB step size accuracy.

SR01453

MAXIMUM ACCUMULATED ERROR

(NOT TO SCALE)

TOP 12 dB FINE STEP ACURACY

BOTTOM 25 dB COARSE STEP AC-

CURACY

+11.5

–3

–15

–26

–28

0

12

24

38

45.9

VGA SETTING (dB)

Figure 11.

Power Control

Oscillator Buffers

There are three buffers for the reference signal, two of which are

used to provide external reference signals. The internal reference

signal is used for the main and auxiliary synthesizer reference. The

second buffer (MCLK) is used as a master clock for external digital

circuitry which is always on, while the third buffer (RCLK) is used as

a clock for external digital circuitry which is not used in sleep mode.

LO Buffers

The LO buffers are used to provide isolation for the VCO and

between the transmitter up-converter and channel synthesizer.