SA9024 datasheet(13/23 Pages) PHILIPS

13 / 23 page

Philips Semiconductors

Objective specification

SA9024

900 MHz transmit modulator and 1.3 GHz

fractional–N synthesizer

1997 Aug 01

SR01449

CLK

(1)

CLK

VCC

TXEN

TEMPORARY REGISTER

SYNEN

(2)

CLOCK

DATA

WORKING REGISTER

STROBE

CLK

(2)

Figure 6.

Transmit Offset Synthesizer Reset Circuit

In Figure 6, the falling edge of the strobe and address, inverted,

toggles the Q output of flip-flop (1) to a ‘1’ state, enabling the phase

detector, VCO, divide by M, TXIF buffer and SSB up-converter.

Approximately 80

µs after the synthesizer is locked, the TXEN signal

(enabled = 1) turns on the modulator and variable gain amplifier.

The rising edge of TXEN has no effect on SYNEN, however, the

falling (rising inverted) edge toggles the Q output of D flip-flop (2) to

a ‘0’ state. This disables the synthesizer, modulator and variable

gain amplifier. To insure that slow edges on TXEN do not cause

improper operation, the TXEN is a Schmitt trigger design.

The address decoder for program word ‘D’ ANDed together with the

strobe is used to load the contents of the temporary register into the

working registers. D flip-flop (3) is used to prevent multiple strobe

and address pulses in the event the address decoder output toggles

on garbage bits during the time the strobe remains in a ‘1’ state.

The temporary register is common to the transmit offset synthesizer,

main channel synthesizer and auxiliary synthesizer.

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