SST25WF080B datasheet(7/44 Pages) MICROCHIP

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DS20005164H-page 7

SST25WF080B

4.2

STATUS Register

The software STATUS register provides status on

whether the flash memory array is available for any

read or write operation, whether the device is write

enabled, and the state of the Memory Write protection.

During an internal erase or program operation, the

STATUS register may be read only to determine the

completion of an operation in progress. Table 4-2

describes the function of each bit in the software STA-

TUS register.

4.2.1

BUSY (BIT 0)

The BUSY bit determines whether there is an internal

Erase or Program operation in progress. A ‘1’ for the

BUSY bit indicates the device is busy with an operation

in progress. A ‘0’ indicates the device is ready for the

next valid operation.

4.2.2

WRITE ENABLE LATCH (WEL–BIT 1)

The Write-Enable Latch bit indicates the status of the

internal Write-Enable Latch memory. If the WEL bit is

set to ‘1’, it indicates the device is Write enabled. If the

bit is set to ‘0’ (reset), it indicates the device is not Write

enabled and does not accept any Write (Program/

Erase) commands. The Write-Enable Latch bit is auto-

matically reset under the following conditions:

• Power-Up

• Write Disable (WRDI) instruction completion

• Page Program instruction completion

• Sector Erase instruction completion

• 64-Kbyte Block Erase instruction completion

• Chip Erase instruction completion

• Write STATUS Register instruction completion

4.2.3

BLOCK PROTECTION (BP0, BP1,

BP2, AND TB–BITS 2, 3, 4, AND 5)

The Block Protection (BP0, BP1, BP2, and TB) bits

define the size of the memory area to be software pro-

tected against any memory Write (Program or Erase)

operation, see Table 4-3. The Write-Status-Register

(WRSR) instruction is used to program the BP0, BP1,

BP2, and TB bits as long as WP# is high or the Block

Protect Lock (BPL) bit is ‘0’. Chip Erase can only be

executed if Block Protection bits are all ‘0’. BP0, BP1,

and BP2 select the protected area and TB allocates the

protected area to the higher-order address area (Top

Blocks) or lower-order address area (Bottom Blocks).

TABLE 4-2:

SOFTWARE STATUS REGISTER

Bit

Name

Function

Default at

Power-up

Read/Write

0BUSY

1 = Internal write operation is in progress

0 = No internal write operation is in progress

1WEL

1 = Device is memory write-enabled

0 = Device is not memory write-enabled

BP0(1)

Indicate current level of block write protection (See Table 4-3)

0 or 1

R/W

BP1(1)

Indicate current level of block write protection (See Table 4-3)

0 or 1

R/W

BP2(1)

Indicate current level of block write protection (See Table 4-3)

0 or 1

R/W

5TB(1)

1 = 1/16, 1/8, 1/4, or 1/2 Bottom Memory Blocks are protected (See Table 4-3)

0 = 1/16, 1/8, 1/4, or 1/2 Top Memory Blocks are protected

0 or 1

R/W

RES

Reserved for future use

N/A

BPL(1)

1 = BP0, BP1, BP2, TB, and BPL are read-only bits

0 = BP0, BP1, BP2, TB, and BPL are read/writable

0 or 1

R/W

Note 1: BP0, BP1, BP2, TB, and BPL bits are non-volatile memory bits.

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