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SST25WF080B 数据表(PDF) 17 Page - Microchip Technology |
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SST25WF080B 数据表(HTML) 17 Page - Microchip Technology |
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17 / 44 page ![]() 2013-2022 Microchip Technology Inc. and its subsidiaries DS20005164H-page 17 SST25WF080B 5.10 Write Enable (WREN) The Write Enable (WREN) instruction, 06H, sets the Write Enable Latch bit in the STATUS Register to ‘1’ allowing write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write STATUS Register (WRSR) instruction; however, the Write Enable Latch bit in the STATUS register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven low before entering the WREN instruction, and CE# must be driven high before executing the WREN instruction. See Figure 5-10 for the WREN instruction sequence. FIGURE 5-10: WRITE ENABLE (WREN) SEQUENCE 5.11 Write Disable (WRDI) The Write Disable (WRDI) instruction, 04H, resets the Write Enable Latch bit to ‘0’, thus preventing any new write operations. CE# must be driven low before enter- ing the WRDI instruction, and CE# must be driven high before executing the WRDI instruction. See Figure 5-11 for the WRDI instruction sequence. FIGURE 5-11: WRITE DISABLE (WRDI) SEQUENCE CE# SO SI SCK 0 1 234 5 6 7 06 High-Impedance MODE 0 MODE 3 MSb CE# SO SI SCK 0 1 234 5 6 7 04 High-Impedance MODE 0 MODE 3 MSb |
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