ADN4600ACPZ-R7 datasheet(5/28 Pages) AD

部件名	ADN4600ACPZ-R7

功能描述	4.25 Gbps, 8 × 8, Asynchronous Crosspoint Switch

PDF	28 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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5 / 28 page

Data Sheet

ADN4600

Rev. C | Page 5 of 28

TIMING SPECIFICATIONS

Table 2. I2C Timing Parameters

Parameter

Min

Max

Unit

Description

fSCL

400

kHz

SCL clock frequency

tHD;STA

0.6

N/A

s

Hold time for a start condition

tSU;STA

0.6

N/A

s

Setup time for a repeated start condition

tLOW

1.3

N/A

s

Low period of the SCL clock

tHIGH

0.6

N/A

s

High period of the SCL clock

tHD;DAT

N/A

s

Data hold time

tSU;DAT

N/A

Data setup time

300

Rise time for both SDA and SCL

300

Fall time for both SDA and SCL

tSU;STO

0.6

N/A

s

Setup time for a stop condition

tBUF

N/A

Bus-free time between a stop and a start condition

CIO

Capacitance for each I/O pin

I2C Timing Specifications

SDA

SCL

tBUF

tLOW

tHD:STA

tHD:DAT

tHIGH

tSU:DAT

tSU:STA

tSU:STO

tHD:STA

Figure 2. I2C Timing Diagram

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