ADN4600ACPZ-R7 datasheet(14/28 Pages) AD

14 / 28 page

ADN4600

Data Sheet

Rev. C | Page 14 of 28

Table 5. Common Input Voltage Levels

Configuration

VCC (V)

VTTI (V)

Low VTTI, AC-Coupled Input

1.8

1.6

Single 1.8 V Supply

1.8

3.3 V Core

3.3

1.8

Single 3.3 V Supply

3.3

Table 6. Receive Equalizer Boost vs. Setting

RX EQ Bit Settings

Boost (dB)

Typical FR4 Trace Length (Inches)

3.5

5 to 10

3.9

10 to 15

4.25

15 to 20

4.5

20 to 25

4.75

25 to 30

5.0

30 to 35

5.3

35 to 40

5.5

35 to 40

Table 7. Equalization Control Registers

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

RX[7:0] Configuration

0xB8, 0xB0,

0xA8, 0xA0,

0x98, 0x90,

0x88, 0x80

RX PNSWAP

RX EQBY

RX EN

RX EQ[2]

RX EQ[1]

RX EQ[0]

0x30

RX[7:0] EQ1 Control

0xBB, 0xB3,

0xAB, 0xA3,

0x9B, 0x93,

0x8B, 0x83

EQ CTL SRC

RX EQ1[5]

RX EQ1[4]

RX EQ1[3]

RX EQ1[2]

RX EQ1[1]

RX EQ1[0]

0x00

RX[7:0] EQ3 Control

0xBC, 0xB4,

0xAC, 0xA4,

0x9C, 0x94,

0x8C, 0x84

RX EQ3[5]

RX EQ3[4]

RX EQ3[3]

RX EQ3[2]

RX EQ3[1]

RX EQ3[0]

0x00

RX[7:0] FR4 Control

0xBD, 0xB5,

0xAD, 0xA5,

0x9D, 0x95,

0x8D, 0x85

RX LUT

select

RX LUT

FR4/CX4

0x00

Lane Inversion

The receiver P/N inversion feature is a convenience intended to

allow the user to implement the equivalent of a board-level

crossover in a much smaller area and without additional via

impedance discontinuities that degrade the high-frequency

integrity of the signal path. The P/N inversion is independent

for each of the eight channels and is controlled through the I2C

control interface.

Warning

Using the lane inversion feature to account for signal inversions

downstream of the receiver requires additional attention when

switching connectivity.

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