ADN4600ACPZ-R7 datasheet(15/28 Pages) AD

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Data Sheet

ADN4600

Rev. C | Page 15 of 28

SWITCH CORE

The ADN4600 switch core is a fully nonblocking 8 × 8 array

that allows multicast and broadcast configurations. The

configuration of the switch core is controlled through the I2C

control interface. The control interface receives and stores the

desired connection matrix for the eight input and eight output

signal pairs. The interface consists of eight rows of double-rank

latches, one for each output. The 2-bit data-word stored in these

latches indicates to which (if any) of the eight inputs the output

will be connected.

One output at a time can be preprogrammed by addressing the

output and writing the desired connection data into the first rank

of latches. This is done by writing to the XPT configuration

into Bits[2:0], and the input being sent to this output is written

into Bits[6:4]. This process can be repeated until each of the

desired output changes has been preprogrammed. Bit 3 of the

XPT configuration register (Address 0x40) signals whether a

broadcast condition is desired. If this bit is set high, the input

selected by Bits[6:4] is sent to all outputs. All output connections

can then be programmed simultaneously by passing the data

from the first rank of latches into the second rank by writing

0x01 to the XPT update register (Address 0x41). This is a self-

clearing register and therefore always reads back as 0x00. The

output connections always reflect the data programmed into the

second rank of latches and do not change until the first rank of data

is passed into the second rank by strobing the XPT update register.

If necessary for system verification, the data in the first rank of

latches can be read back from the control interface. This is done

by reading from the XPT Temp[3:0] registers, which show the

status of the input data programmed in the first rank of latches

for each output.

Table 8. Switch Core Control and Status Registers

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

XPT Configuration

0x40

IN PORT

[2]

IN PORT

[1]

IN PORT

[0]

Broadcast

OUT PORT

[2]

OUT PORT

[1]

OUT PORT

[0]

0x00

XPT Update

0x41

Update

0x00

XPT Status 0

0x50

OUT0[2]

OUT0[1]

OUT0[0]

N/A

XPT Status 1

0x51

OUT1[2]

OUT1[1]

OUT1[0]

N/A

XPT Status 2

0x52

OUT2[2]

OUT2[1]

OUT2[0]

N/A

XPT Status 3

0x53

OUT3[2]

OUT3[1]

OUT3[0]

N/A

XPT Status 4

0x54

OUT4[2]

OUT4[1]

OUT4[0]

N/A

XPT Status 5

0x55

OUT5[2]

OUT5[1]

OUT5[0]

N/A

XPT Status 6

0x56

OUT6[2]

OUT6[1]

OUT6[0]

N/A

XPT Status 7

0x57

OUT7[2]

OUT7[1]

OUT7[0]

N/A

Table 9. Switch Core Temporary Registers

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

XPT Temp 0

0x58

OUT1[2]

OUT1[1]

OUT1[0]

OUT0[2]

OUT0[1]

OUT0[0]

N/A

XPT Temp 1

0x59

OUT3[2]

OUT3[1]

OUT3[0]

OUT2[2]

OUT2[1]

OUT2[0]

N/A

XPT Temp 2

0x5A

OUT5[2]

OUT5[1]

OUT5[0]

OUT4[2]

OUT4[1]

OUT4[0]

N/A

XPT Temp 3

0x5B

OUT7[2]

OUT7[1]

OUT7[0]

OUT6[2]

OUT6[1]

OUT6[0]

N/A

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