ADN4600ACPZ-R7 datasheet(22/28 Pages) AD

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ADN4600

Data Sheet

Rev. C | Page 22 of 28

I2C CONTROL INTERFACE

Serial Interface General Functionality

The ADN4600 register set is controlled through a 2-wire I2C

interface. The ADN4600 acts only as an I2C slave device. Therefore,

the I2C bus in the system needs to include an I2C master to

configure the ADN4600 and other I2C devices that may be on

the bus. Data transfers are controlled by the two I2C wires: the

SCL input clock pin and the SDA bidirectional data pin.

The ADN4600 I2C interface can be run in the standard (100 kHz)

and fast (400 kHz) modes. The SDA line only changes value

when the SCL pin is low, with two exceptions: the SDA pin is

driven low while the SCL pin is high to indicate the beginning

or continuation of a transfer, and the SDA line is driven high

while the SCL line is high to indicate the end of a transfer.

Therefore, it is important to control the SCL clock to toggle

only when the SDA line is stable, unless indicating a start,

repeated start, or stop condition.

I2C Interface Data Transfers: Data Write

To write data to the ADN4600 register set, a microcontroller

(or any other I2C master) needs to send the appropriate control

signals to the ADN4600 slave device. Use the following steps,

where the signals are controlled by the I2C master unless otherwise

specified. A diagram of the procedure is shown in Figure 31.

Send a start condition (that is, while holding the SCL line

high, pull the SDA line low).

Send the ADN4600 part address (seven bits), whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the ADDR1 and ADDR0 input pins.

This transfer should be MSB first.

Send the write indicator bit (0).

Wait for the ADN4600 to acknowledge the request.

Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

Wait for the ADN4600 to acknowledge the request.

Send the data (eight bits) to be written to the register

whose address was set in Step 5. This transfer should be

MSB first.

Wait for the ADN4600 to acknowledge the request.

Send a stop condition (that is, while holding the SCL line

high, pull the SDA line high) and release control of the bus.

10. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 in this procedure to perform another write.

11. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 of the read procedure (see the I2C Interface Data

Transfers: Data Read section) to perform a read from

another address.

12. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 8 of the read procedure (in the I2C Interface Data

Transfers: Data Read section) to perform a read from the

same address set in Step 5 of the write procedure.

In Figure 31, the ADN4600 write process is shown. The SCL

signal is shown, along with a general write operation and a

specific example. In the example, Data 0x92 is written to Register

Address 0x6D of an ADN4600 part with a slave address of 0x4B.

The slave address is seven bits wide. The upper five bits of the

slave address are internally set to b10010. The lower two bits

are controlled by the ADDR[1:0] pins. In this example, the bits

controlled by the ADDR[1:0] pins are set to b11. In the figure,

the corresponding step number is visible in the circle under the

waveform. The SCL line is driven by the I2C master, not by the

ADN4600 slave. As for the SDA line, the data in the shaded

polygons of Figure 31 is driven by the ADN4600, whereas the

data in the nonshaded polygons is driven by the I2C master. The

end phase case shown corresponds with Step 9.

It is important to note that the SDA line only changes when

the SCL line is low, except when a start, stop, or repeated start

condition is being sent, as is the case in Step 1 and Step 9.

SCL

SDA

GENERAL CASE

EXAMPLE

START

ACK

STOP

DATA

R/W

FIXED PART ADDR

ADDR

[1:0]

Figure 31. I2C Write Diagram

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