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IP1202PBF 数据表(PDF) 17 Page - International Rectifier

部件名 IP1202PBF
功能描述  Dual Output Full Function 2 Phase Synchronous Buck Power Block Integrated Power Semiconductors, PWM Control & Passives
PDF  29 Pages
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制造商  IRF [International Rectifier]
网页  http://www.irf.com
标志 IRF - International Rectifier

IP1202PBF 数据表(HTML) 17 Page - International Rectifier

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17
iP1202PbF
For better efficiency and low input ripple, select low
ESR ceramic capacitors. The amount of the capaci-
tors is determined based on the r.m.s. rating. In the
above example, a total of 4 x 22µF, 2A capacitors will
be required to support the input r.m.s. current, includ-
ing derating (see the parts list in the reference de-
sign section of this datasheet).
The 18out of phase operation of the iP1202PbF
provides reduced voltage ripple at the input of the
device. This reduction in ripple requires less input
bypass capacitance.
For single output configuration and a duty cycle
greater than 0.5, select the input capacitors accord-
ing to equation (4) :
D is the duty cycle and is expressed as:
D = V
OUT / VIN.
Output Capacitor CO Selection
Selection of the output capacitors depends on two
factors:
a. Low effective ESR for ripple and load transient re-
quirements
To support the load transients and to stay within a
specified voltage dip ∆V due to the transients, e.s.r.
selection should satisfy equation (5):
R
esr ≤ ∆V / ILoadmax
(5)
Where,
I
Loadmax is the maximum load current.
If output voltage ripple is required to be maintained
at specified levels then, the expression in equation
(6) should be used to select the output capacitors.
R
esr ≤ Vp-p / Iripple
(6)
Where,
V
p-p is the single phase peak to peak output voltage
ripple.
I
ripple is the inductor current peak-to peak ripple.
In addition, the voltage ripple caused by the output
capacitor needs to be significantly smaller than the
ripple caused by the ESR of the capacitor. Use equa-
tion (7) to satisfy this requirement.
If the inductor current ripple I
ripple is 30% of IOUT1, the
50mV peak to peak output voltage ripple requirement
will be met if the total e.s.r. of the output capacitors is
less than 11mΩ. This will require 2 x 470µF POSCAP
capacitors (See the parts list in the reference design
section of this datasheet). Additional ceramic capaci-
tors can be added in parallel to further reduce the
e.s.r. Care should be given to properly compensate
the control loop for low output capacitor e.s.r. values.
When selecting output capacitors, it is important to
consider the overshoot performance of the power sup-
ply. If the amount of capacitance is not adequate, then,
when unloading the output, the magnitude of the over-
shoot due to stored inductor energy, and depending
on the speed of the response of the control loop, can
exceed the overvoltage trip threshold of the
iP1202PbF and can cause undesirable shutdown of
the output. The magnitude of the overshoot should
be kept below 1.125V
OUT . To prevent the overshoot
from tripping the output a delay can be added by in-
stalling capacitor C26 as shown in Fig.17.
In paralleled single output configuration, due to 180°
phase shift, the peak to peak output voltage ripple
will be reduced because of doubling of the ripple fre-
quency. Also, the resulting ripple current in the out-
put capacitors will be smaller than the ripple current
of each channel. There is some cancellation effect of
these current, the magnitude of which depends on
the duty cycle.
b. Stability
The value of the output capacitor e.s.r. zero frequency
f
esr plays a major role in determining stability. fesr is
calculated by the expression in equation (8).
f
esr = 1 / (2 π x Resr x CO)
(8)
Details on how to consider this parameter to design
for stability will be outlined in the control loop com-
pensation section of this datasheet.
Inductor LO Selection
Inductor selection is based on trade-offs between size
and efficiency. Low inductor values result in smaller
sizes, but can cause large ripple currents and lower
efficiency. Low inductor values also benefit the tran-
sient performance.
esr
s
o
R
f
C
>
π
2
10
(7)
(4)
()
1
2
)(
2
2
(
=
D
D
I
I
LOAD
RMS



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