IP1202PBF datasheet(16/29 Pages) IRF

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iP1202PbF

Only a few external components are required to com-

plete a dual output synchronous buck power supply

using iP1202PbF. The following procedure will guide

the designer through the design and selection pro-

cess of these external components.

A typical application for iP1202PbF will be:

IN = 12V, VOUT1 = 1.5V, IOUT1 = 15A, VOUT2 = 2.5V, IOUT2

= 10A, f

sw = 300kHz, Vp-p1 = Vp-p2 = 50mV

Setting the Output Voltage

The output voltage of the iP1202PbF is set by the

0.8V reference Vref and external voltage dividers.

Fig. 17: Typical scheme for output voltage setting

OUT1 is set according to equation (1):

OUT1 = Vref x (1 + R9 /R7 ) (see Fig. 17)

(1)

Setting R

7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will

result in R

9= 875 ohms (select 887 ohms). Final val-

ues can be selected according to the desired accu-

racy of the output.

To set the output voltage for Type III compensation,

refer to equation (25) in Type III compensation sec-

tion.

If the 0.8V reference is used to set the voltage for the

second output V

OUT2, VP-ref pin must be shorted to

Vref pin and in a similar way, voltage divider resistors

are selected for the second output V

OUT2. The second

output can also be set by applying an external refer-

iP1202PbF Design Procedure

ence source to VP-ref. In this case, to ensure proper

start-up, power to VP-ref and iP1202PbF must be

applied simultaneuosly.

Setting the Overvoltage Trip

Both outputs of the iP1202PbF will shut down if ei-

ther one of the outputs experiences a voltage in the

range of 115% of V

OUT. The overvoltage sense pins

FB1s and FB2s are connected to the output through

voltage dividers, R

13 and R14 (Fig. 17), and the trip

setpoints are programmed according to equation (1).

Separate overvoltage sense pins FB1

s and FB2s are

provided to protect the power supply output if for some

reason the main feedback loop is lost (for instance,

loss of feedback resistors). An optional 100pF ca-

pacitor (C26) is used for delay and filtering purposes.

If this redundancy is not required and if Type II con-

trol loop compensation scheme is utilized, FB1s and

FB2s pins can be connected to FB1 and FB2 pins

respectively.

In parallel configuration, FB2s should be connected

to FB1s

Setting the Soft-Start Capacitor

The soft start capacitor C

ss is selected according to

equation (2):

ss = 40 x Css

(2)

where,

ss is the output voltage ramp time in milliseconds,

and C

ss is the soft start capacitor in µF.

A 0.1µF capacitor will provide an output voltage ramp-

up time of about 4ms.

Input Capacitor Selection

The switching currents impose RMS current require-

ments on the input capacitors. The expression in

equation (3) allows the selection of the input capaci-

tors for duty cycles less than 0.5:

where, I

1 and I2 are the load currents for outputs 1

and 2 respectively and D

1 and D2 are the duty cycles

for channel 1 and channel 2 respectively.

For output1 of the above example D= 0.13 and,

For output2 of the above example D = 0.21 and,

For the above example, using equation (3) the ca-

pacitor rms current yields 5.8A.

R13

R14

iP1202

C26

(Optional)

Vout1

FB1

FB1S

For Type II compensation,

()

)

(

)

(

RMS

−

(3)

iP1202PbF

IP1202PBF 数据表(PDF) 16 Page - International Rectifier

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