IP1202PBF datasheet(25/29 Pages) IRF

25 / 29 page

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iP1202PbF

For stable and noise free operation of the whole

power system, it is recommended that the designer

uses the following guidelines:

1. Follow the layout scheme presented in Fig. 32.

Make sure that the output inductors L1 and L2 are

placed as close to iP1202PbF as possible to pre-

vent noise propagation that can be caused by

switching of power at the switching node Vsw, to

sensitive circuits.

2. Provide a mid-layer solid ground plane with con-

nections to the top layer through vias. The PGND

pads of iP1202PbF also need to be connected to

the same ground plane through vias.

3. To increase power supply noise immunity, place

input and output capacitors close to one another,

as shown in the layout diagram. This will provide

short high current paths that are essential at the

ground terminals.

4. Although there is a certain degree of V

IN bypass-

ing inside the iP1202PbF, the external input

decoupling

capacitors should be as close to the device as pos-

sible.

5. The Feedback tracks from the outputs V

OUT1 and

OUT2 to FB1 and FB2 respectively, should be routed

as far away from noise generating traces as pos-

sible.

6. The compensation components and the Vref by-

pass capacitor should be placed as close as pos-

sible to their corresponding iP1202PbF pins.

7. For single output configuration, the parasitic paths

leading to the common output connector from each

parallel branch should be symmetrically routed to

ensure equal current sharing.

8. Refer to IR application note AN-1029 to deter-

mine what size vias and copper weight and thick-

ness to use when designing the PCB.

9. Place the overcurrent threshold setting resistors

OCSET1 and ROCSET2 close to the iP1202PbF block at

the corresponding connection nodes.

Layout Guidelines

Fig. 31: iP1202PbF suggested layout

IP1202PBF 数据表(PDF) 25 Page - International Rectifier

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