IP1202PBF datasheet(13/29 Pages) IRF

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iP1202PbF

The dual output PWM controller inside the iP1202PbF

provides a 180° out of phase operation of the PWM

outputs. This method of control offers the advantage

of reducing the amount of input bypass capacitors

due to increase in input ripple frequency and hence

reduction of ripple amplitude. Moreover, for paralleled

output configurations 180° phase shifting contributes

to smaller output capacitors due to output inductor

ripple current cancellation and ripple reduction.

The operating switching frequency (f

SW) range of

iP1202PbF is 200 kHz to 400 kHz. The desired fre-

quency is set by placing an external resistor to the

RT pin of the iP1202PbF. See Fig. 9 for the proper

resistor value.

The iP1202PbF is capable of accepting an external

digital synchronization signal. Synchronization will

be enabled by the rising edge clock. The free run-

ning oscillator frequency is twice the per-channel fre-

quency. During synchronization, RT is selected such

that the free running frequency is 20% below the

synchronization frequency. The maximum synchro-

nization frequency that iP1202PbF can accept is

800kHz. Note that the actual free running frequency

of individual output is half the synchronization fre-

quency.

Overcurrent Protection/Autorestart

The Overcurrent Protection function of the

iP1202PbF offers two distinct modes: HICCUP of the

output and Overcurrent Shutdown. If the Hiccup pin

is pulled high (Hiccup enabled), hiccup mode will be

selected. If Hiccup pin is pulled low (Hiccup dis-

abled), overcurrent shutdown will be selected.

During overloads, in HICCUP disabled mode, the

controller shuts down as soon as the trip threshold

is reached. In HICCUP enabled mode, when

overcurrent trip threshold is reached, the power sup-

ply output shuts down and attempts to restart. The

time duration between the shutdown of the output

and the restart is determined by the time it takes to

discharge the soft start capacitor. Typically, the dis-

charge time of the soft start capacitor is 10 times the

charge time. The duty cycle of the hiccup

process is typically 5%. The output will stay in hic-

cup indefinitely until the overload is removed. The

typical overcurrent trip threshold of the device is

internally set at 30A. The overcurrent shutdown / HIC-

CUP threshold is ±30% accurate.

The iP1202PbF overcurrent shutdown and HICCUP

threshold can be set externally by adding R

OCSET1 and

OCSET2 resistors from OCSET1 and OCSET2 pins to

VSW1 and VSW2 pins respectively. Refer to Fig.8

for R

OCSET1 and ROCSET2 selection.

Overvoltage Protection (OVP)

Overvoltage is sensed through separate output volt-

age sense pins FB1s and FB2s. A separate OVP

circuit is provided for each output and the OVP

threshold is set to 115% of the output voltage. Upon

overvoltage condition of either one of the outputs,

the OVP forces a latched shutdown on both outputs.

In this mode, the upper FETs turn off and the lower

FETs turn on, thus crowbaring the outputs. Reset is

performed by recycling the ENABLE pin. Overvolt-

age can be sensed by either connecting FB1s and

FB2s to their corresponding outputs through sepa-

rate output voltage divider resistor networks, or they

can be connected directly to their corrsponding feed-

back pins FB1 and FB2. For Type III control loop

compensation, FB1s and FB2s should be connected

through voltage dividers only.

the inductor current information for current sharing.

In this mode, VP-ref pin must be disconnected from

Vref pin and connected to the output of channel1

inductor, see Fig. 15. The inductor current informa-

tion is provided through external shunts placed in

series with the output inductors.

A lossless inductor current sensing scheme can also

be implemented as shown in Fig.16, where the cur-

rent is sensed through the DC resistance of the in-

ductor. In this case R

L and CL are selected such that

Lx CL = L / Rdc. Set RL = 1K and solve for CL. Rdc is

the internal DC resistance of inductor L.

In single output two phase mode, leave SS2 pin

open.

The iP1202PbF can also be configured in dual out-

put tracking mode where the second output tracks

the

first output.

For a specific output configuration, follow the con-

nection diagram shown in Fig.14, Fig.15, Fig.16 at

the end of this section.

Out of Phase Operation

Frequency and Synchronization

Synchronization capability is provided both in inde-

pendent and parallel configurations. When unused,

the SYNC pin must be left floating.

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