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LP1072 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

部件名 LP1072
功能描述  802.11a/b/g Baseband System Solution
PDF  32 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

LP1072 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

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LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
21
PRELIMINARY
IADCINN
pdiana2p
Input
Negative input of I-ADC
A8
IADCINP
pdiana2p
Input
Positive input of I-ADC
B8
QADCINN
pdiana2p
Input
Negative input of Q-ADC
B6
QADCINP
pdiana2p
Input
Positive input of Q-ADC
C6
RSSIADCIN
pdiana2p
Input
RSSI ADC input
B1
VOCM
pdiana2p
Input
Input pin for definition of IQDAC output common -mode level
D9
AUXDACOUT
pdiana2p
Output
Auxiliary DAC output
C4
IDACOUTP
pdiana2p
Output
Positive output of I-DAC
B9
IDACOUTN
pdiana2p
Output
Negative output of I-DAC
C9
QDACOUTP
pdiana2p
Output
Positive output of Q-DAC
B10
QDACOUTN
pdiana2p
Output
Negative output of Q-DAC
A10
EXT_BIAS
pdiana2p
Input
External Bias for test
D4
TCXO Squarer
AVDD_TCXO
pvdd3p
N/A
Analog 3.3 volt
F4
AVSS_TCXO
pvss3p
N/A
Analog ground
G5
CLKIN
pdiana2p
Input
TCXO reference clock input
F1
RF Interface Signals
RF_ANALOG_LDO
pdb04dgz
Bi-dir
LDO enable for RF VCO power. Driven by PHY controller.
M9
RF_EN
pdb04dgz
Bi-dir
RF enable. Driven by PHY controller.
R12
RF_RXEN
pdb04dgz
Bi-dir
RF Rx enable. Driven by PHY controller.
P11
RF_TXEN
pdb04dgz
Bi-dir
RF Tx enable. Driven by PHY controller.
N13
RF_PAEN1
pdb04dgz
Bi-dir
RF PA enable 1. Driven by PHY controller.
P14
RF_PAEN2
pdb04dgz
Bi-dir
RF PA enable 2. Driven by PHY controller.
M13
RF_SPARE1
pdb04dgz
Bi-dir
RF spare 1 (not used). Driven by PHY controller.
L12
RF_SPARE2
pdb04dgz
Bi-dir
RF spare 2 (not used). Driven by PHY controller.
G13
RF_VGA6
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
M14
RF_VGA5
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
N15
RF_VGA4
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
M15
RF_VGA3
pdo02cdg
Output
RF VGA setting. Driven by UWA.
K13
RF_VGA2
pdo02cdg
Output
RF VGA setting. Driven by UWA.
L14
RF_VGA1
pdo02cdg
Output
RF VGA setting. Driven by UWA.
L15
RF_VGA0
pdo02cdg
Output
RF VGA setting. Driven by UWA.
J13
RF_RXHP
pdo02cdg
Output
RF Rx highpass filter setting. Driven by UWA.
H12
RF_ANTENNA_SEL
pdo02cdg
Output
RF antenna select. Driven by ARM.
H13
RF_ANTENNA_SEL_N
pdo02cdg
Output
RF antenna select. Driven by ARM.
J15
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
Description
Pin



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