LP1072 Advance Information, Rev. 0.3

2

Freescale Semiconductor

PRELIMINARY

Introduction

terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes

to power consumption and performance.

1.2

General Description

The high-performance LP1072 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC

functionality with the industry’s lowest power consumption compared to any baseband processor in the

market.

The LP1072 was designed to target embedded devices and small form factor WLAN devices. Its support

for SDIO and CompactFlash+ host interfaces combined with its ultra low power consumption and small

size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that

lets it interface with virtually any RF components in the market. It has been fully tested to interface with

RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in

selecting the most appropriate RF parts based on their application and form factor.

The LP1072’s integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall

system cost. The integrated internal memory eliminates the need for external MAC memory, further

reducing cost and saving valuable board space for small form factor devices.

The LP1072 also provides the highest level of WLAN security by fully supporting WPA and AES.

1.3

Features

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Full compliance with 802.11a/b/g

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Ultra low power consumption, maximizing battery life and minimizing heat dissipation

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Ultra small package: 13.0 x 13.0 x 1.0 (max) mm

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Fully embedded ARM7TDMI™ microprocessor for no load on the host processor, leading to

maximum flexibility in supporting different host platforms

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Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications

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Support for WPA and AES, for enhanced security

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Automatic power management to reduce power consumption

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On-chip ADC and DAC to reduce system BOM and save on board area

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On-Chip PLL for clock generation

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On-chip ROM/RAM eliminating the need for external MAC memory

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Direct memory access (DMA) to reduce CPU utilization

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High throughput achieved using DMA

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Support of SDIO host interface

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Support of CompactFlash host interface

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Support of 16-bit SRAM emulation mode

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Serial EEPROM interface for initialization and device booting

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Eight General Purpose I/O (GPIO) pins for added flexibility

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UART interface to support diagnostic tools and general data transfer