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LP1072 数据表(PDF) 18 Page - Freescale Semiconductor, Inc |
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LP1072 数据表(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 32 page  LP1072 Advance Information, Rev. 0.3 18 Freescale Semiconductor PRELIMINARY Pinout and Footprint AVDD_PLL pdiana2p N/A Analog 1.8 volt C1 AVSS_PLL pdiana2p N/A Analog ground D1 TAVDDPOWER pvdd3p N/A 3.3 volt power for ESD Diodes E3 DVDD_PLL pdiana2p N/A 1.8 volt digital power for PLL E1 DVSS_PLL pdiana2p N/A 1.8 volt digital ground for PLL E2 TXCO_BYPASS pdidgz Input Bypass the TCXO and use the TCXO_BYPASS_CLK C11 TXCO_BYPASS_CLK pdidgz Input TCXO bypass clock D11 XTAL_BYPASS pdidgz Input Bypass XTAL osc and use XTAL_BYPASS_CLK D15 XTAL_BYPASS_CLK pdidgz Input XTAL bypass clock D13 FAST_CLK_POWER pdo02cdg Output Enable the TCXO C10 XTAL_32K_XIN pdxoe4dg Analog 32kHz crystal (NOTE: Must be placed next to PVDD1DGZ.) C15 XTAL_32K_XOUT Analog 32kHz crystal C14 RESET_N pdisdgz Input Chip Reset E13 CHIP_MODE0 pdidgz Input Chip Mode Select 0000 = SDIO normal operation 0001 = CF+ normal operation All other modes are reserved G2 CHIP_MODE1 pdidgz Input J1 CHIP_MODE2 pdidgz Input H3 CHIP_MODE3 pdidgz Input K1 JTAG JTAG_RESET pdudgz Input Tap reset P8 JTAG_CLOCK pdisdgz Input Tap clock M8 JTAG_DI pdudgz Input Tap data in R10 JTAG_DO pdo02cdg Output Tap data out N10 JTAG_MODE pdudgz Input Tap Mode R11 ARM Sub-system Signals ARM_GPIO0 pdb04dgz Bi-dir General Purpose I/O R1 ARM_GPIO1 pdb04dgz Bi-dir General Purpose I/O N3 ARM_GPIO2 pdb04dgz Bi-dir General Purpose I/O R3 ARM_GPIO3 pdb04dgz Bi-dir General Purpose I/O N4 ARM_GPIO4 pdb04dgz Bi-dir General Purpose I/O P4 ARM_GPIO5 pdb04dgz Bi-dir General Purpose I/O N5 ARM_GPIO6 pdb04dgz Bi-dir General Purpose I/O P5 ARM_GPIO7 pdb04dgz Bi-dir General Purpose I/O R5 ARM_UART_0_DI pdb04dgz Input UART input data N7 ARM_UART_0_DO pdb04dgz Output UART output data P6 ARM_EEPROM_DAT_GPIO pdb04dgz Bi-dir General Purpose I/O dedicated for EEPROM M7 Table 9. Pin Description (continued) Pad Name Pad Type Direction Description Pin |
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