LP1072 Interfaces

LP1072 Advance Information, Rev. 0.3

Freescale Semiconductor

15

PRELIMINARY

4.2

CompactFlash+ Host Interface

The LP1072 supports CF+ and Compact Flash Specification Revision 2.0. The LP1072 CF host interface

supports both the I/O and storage modes of the Compact Flash Specifications. The interface allows an

external host (or an host DMA) to have 8-bit or 16-bit memory and I/O mode access to the device

according to the Compact Flash Specification 2.0.

4.3

SRAM Emulation Mode

The SRAM emulation mode provides an alternative write/read access to the device without using the CF

port (or SDIO) using generic SRAM access cycles. It supports 16-bit memory interface.

This mode is host-dependent and can be enabled and tested for a specific host.

4.4

RF Interface

4.4.1

Serial Programmable Interface (SPI)

•

The SPI is composed of 3 signals:

1. RF_SIF_0_SCLK (serial clock)

2. RF_SIF_1_CS_N (chip select)

3. RF_SIF_2_DIN (data input)

•

The serial information is sent to the RF transceiver in 18 bit bursts framed by chip select. The 18

bits comprises of leading 14 (or less) data bits and trailing 4 address bits

•

Programming clock edges are ignored until chip select goes active low.

•

All bits are shifted in on the rising edge of the clock and latched in when chip select returns inactive

high. (permissible for the clock in either state)

•

The interface can be programmed in any operating mode.

•

Serial information is clocked in with the most significant bit (MSB) first.

•

The address bits for the internal registers are decoded on the rising edge of chip select.

•

The rising edge of chip select initiates an internal parallel load pulse that latches the last 18-bit

serially shifted-in data into the internal register.

8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF)

7:0

Imem_rdat[15:0]

This is an internal memory buffer for specific use

by the SDIO device. Data is read or written to this

memory via SDIO cmd 53 reads or writes. Then,

the SDIO DMA controller is used to move the data

from the internal memory buffer to/from shared

memory under device (ARM) control.

-

⎯

RW

-

⎯

Table 8. SDIO Function 1 Registers (continued)

Bit

Name

Description

ARM

Access

HOST

Access

Reset