TDF8541JSSLASHN2 datasheet(23/54 Pages) NXP

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TDF8541

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Product data sheet

Rev. 3 — 13 December 2011

23 of 54

NXP Semiconductors

TDF8541

I2C-bus controlled 4

 45 W power amplifier

8.1 I2C-bus instruction bytes

I2C-bus mode:

• If R/W bit = 0, the TDF8541 expects four instruction bytes; IB1, IB2, IB3, IB4

• After a power-on reset, all instruction bits are set to zero

Legacy mode:

Fig 17. Bit transfer

001aam704

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 18. I2C-bus read and write modes

001aam705

ACK

MSB

− 1

MSB

− 1

LSB + 1

LSB

LSB + 1

78912

789

78912

789

: generated by master (microcontroller)

to stop the transfer, after the last acknowledge (A)

a stop condition (P) must be generated

to stop the transfer, the last byte must not be acknowledged

and a stop condition (P) must be generated

: generated by slave

: start

: stop

: acknowledge

: read / write

R/W

SCL

SDA

SCL

SDA

ACK

MSB

− 1

MSB

− 1

LSB + 1

LSB

LSB + 1

ACK

ADDRESS

WRITE DATA

READ DATA

ADDRESS

I2C-bus WRITE

I2C-bus READ

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