TDF8541JSSLASHN2 datasheet(35/54 Pages) NXP

35 / 54 page

TDF8541

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 13 December 2011

35 of 54

NXP Semiconductors

TDF8541

I2C-bus controlled 4

 45 W power amplifier

t(start-Vo(off))

engine start to output off

time

VP from 14.4 V to 5 V in 1.5 ms;

Vo <0.5 V; see Figure 6

-0.1

t(start-SVRoff)

engine start to SVR off time VP from 14.4 V to 5 V in 1.5 ms;

VSVR < 0.7 V; see Figure 6

4075ms

I2C-bus interface[3]

VIL

LOW-level input voltage

pins SCL and SDA

1.5

VIH

HIGH-level input voltage

pins SCL and SDA

2.3

5.5

VOL

LOW-level output voltage

pin SDA; IL = 5 mA

0.4

fSCL

SCL clock frequency

400

kHz

VADSEL

voltage on pin ADSEL

I2C-bus address

A[6:0] = 1101 101

RADSEL = 0 

RseriesADSEL = 100 k

II(ADSEL)

input current on pin ADSEL VSTB =5V; VADSEL =5V

A

RADSEL

resistance on pin ADSEL

I2C-bus address

A[6:0] = 1101 110

100

101



I2C-bus address

A[6:0] = 1101 111

29.7

30.3



I2C-bus address

A[6:0] = 1101 010

9.9

10.1



legacy mode

0.47



VP(latch)

latch supply voltage

will not react to address selection

changes

Start-up diagnostics

tsudiag

start-up diagnostic time

from start-up diagnostic

command via I2C-bus until

completion of start-up diagnostic;

VO + < 0.1 V; VO  < 0.1 V (no

load) IB1[D1] = 1; see Figure 12

130

250

td(sudiag-on)

start-up diagnostic to on

delay time

at 90 % of output signal;

IB1[D0:D1] = 11; see Figure 12

-680

Voffset

offset voltage

startup diagnostic offset voltage

under no load condition

1.32

2.5V

RLdet(sudiag)

start-up diagnostic load

detection resistance

VP = 14.4 V

shorted load:

high gain; IB3[D6:D5] = 00

0.5



low gain; IB3[D6:D5] = 11

1.5



normal load:

high gain (IB3[D6:D5] = 00)

1.5



low gain (IB3[D6:D5] = 11)

3.2



line driver load

200



open load

400



Table 20.

Characteristics …continued

Refer to test circuit (see Figure 29) at Tamb =25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb =25 C;

guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TDF8541JS/N2 数据表(PDF) 35 Page - NXP Semiconductors

TDF8541JS/N2 数据表(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载

链接网址

TDF8541JS/N2 数据表(PDF) 35 Page - NXP Semiconductors

TDF8541JS/N2 数据表(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表 下载

链接网址

数据表下载