CS8416-CSZ datasheet(34/60 Pages) CIRRUS

34 / 60 page

DS578F3

CS8416

12.2 I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There

is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be con-

nected through a resistor to VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting

a 47 k

Ω resistor from the GPO2 pin to VL or to DGND. The states of the pins are sensed while the CS8416

is being reset.

The signal timings for a read and write cycle are shown in Figures 12 and 13. A Start condition is defined

as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is

high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8416 after a Start

condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 4

bits of the 7-bit address field are fixed at 0010. To communicate with a CS8416, the chip address field, which

is the first byte sent to the CS8416, should match 0010 followed by the settings of the AD2, AD1, and AD0

pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte includes the Mem-

ory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the

contents of the register pointed to by the MAP will be output. The MAP automatically increments, so data

from successive registers will appear consecutively. Each byte is separated by an acknowledge bit (ACK).

The ACK bit is output from the CS8416 after each input byte is read, and is input to the CS8416 from the

microcontroller after each transmitted byte.

Note that the read operation can not set the MAP, so an aborted write operation is used as a preamble. As

shown in Figure 13, the write operation is aborted after the acknowledge for the MAP byte by sending a stop

condition.

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 0 1 0 AD2 AD1 AD0 0

SDA

6 5 4 3 2 1 0

1 0

7 6

1 0

16 17 18 19

10 11

13 14 15

27 28

DATA +n

Figure 12. Control Port Timing, I²C Slave Mode Write

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

SDA

CHIP ADDRESS (READ)

START

3 2 1 0

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18 19

ACK

DATA + n

STOP

0 0 1 0 AD2 AD1 AD0 0

0 0 1 0 AD2 AD1 AD0 1

Figure 13. Control Port Timing, I²C Slave Mode Read

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