CS8416-CSZ datasheet(41/60 Pages) CIRRUS

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DS578F3

CS8416

SOLRPOL

- OLRCK clock polarity

Default = ‘0’

0 - SDOUT data is valid for the left channel when OLRCK is high.

1 - SDOUT data is valid for the right channel when OLRCK is high.

14.8 Receiver Error Mask (06h)

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask

bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register,

will affect RERR, will affect the RERR interrupt, and will affect the current audio sample according to the

status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not

appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will

not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they

do not affect the current audio sample even when unmasked. This register defaults to 00h.

14.9 Interrupt Mask (07h)

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error

is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set

to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg-

ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to

00h.

The INT signal may be selected to output on the GPO pins. See “General Purpose Outputs” on page 29.

14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are

three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active

mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode,

the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt

pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only

depends on the INT[1:0] bits. These registers default to 00h.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

76543210

QCRCM

CCRCM

UNLOCKM

CONFM

BIPM

PARM

76543210

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

76543210

PCCH1

OSLIP1

DETC1

CCH1

RERR1

QCH1

FCH1

PCCH0

OSLIP0

DETC0

CCH0

RERR0

QCH0

FCH0

CS8416-CSZ 数据表(PDF) 41 Page - Cirrus Logic

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