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CS8416-CSZ 数据表(PDF) 39 Page - Cirrus Logic |
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CS8416-CSZ 数据表(HTML) 39 Page - Cirrus Logic |
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39 / 60 page ![]() DS578F3 39 CS8416 14.5 Control3 (03h) GPO1SEL[3:0] – GPO1 Source select. See “General Purpose Outputs” on page 29. Default = ‘0000’ GPO2SEL[3:0] – GPO2 Source select. See “General Purpose Outputs” on page 29. Default = ‘0000’ 14.6 Control4 (04h) RUN - Controls the internal clocks, allowing the CS8416 to be placed in a “powered down”, low current con- sumption state. Default = ‘0’ 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Power consumption is low. 1 - Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. RXD – RMCK Control Default = ‘0’ 0 -RMCK is an output, Clock is derived from input frame rate. 1 – RMCK becomes high impedance. The output of OSCLK, OLRCK, and SDOUT are indeterminate. RX_SEL[2:0] – Selects RXP0 to RXP7 for input to the receiver Default =’000’ 000 – RXP0 001 – RXP1, etc 7 6 5 4 3210 GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL0 GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL0 76543210 RUN RXD RXSEL2 RXSEL1 RXSEL0 TXSEL2 TXSEL1 TXSEL0 Figure 14. De-Emphasis Filter Response F2 F1 -10 3.183 Frequency, KHz T1 = 50us 0 10.61 Gain, dB T2 =15us |
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