AS7C1024C

12/5/06, v. 1.0

Alliance Memory

P. 2 of 9

®

Functional description

The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized

as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing

are desired.

performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank

systems.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0

through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2).

To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE)

or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.

The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable

is inactive, or write enable is active, output drivers stay in high-impedance mode.

Note:

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Key: X = don’t care, L = low, H = high.

Absolute maximum ratings

Parameter

Symbol

Min

Max

Unit

–0.50

+7.0

V

Voltage on any pin relative to GND

–0.50

V

Power dissipation

–1.25

W

Storage temperature (plastic)

–55

+125

°C

–55

+125

°C

DC current into outputs (low)

–50

mA

Truth table

CE1

CE2

WE

OE

Data

Mode

H

X

X

X

High Z

X

L

X

X

High Z

L

H

H

H

High Z

LH

H

L

LH

L

X