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AS7C1024C 数据表(PDF) 4 Page - Alliance Semiconductor Corporation

部件名 AS7C1024C
功能描述  5V 128K X 8 CMOS SRAM
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ALSC [Alliance Semiconductor Corporation]
网页  https://www.alliancememory.com
标志 ALSC - Alliance Semiconductor Corporation

AS7C1024C 数据表(HTML) 4 Page - Alliance Semiconductor Corporation

  AS7C1024C Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C1024C Datasheet HTML 9Page - Alliance Semiconductor Corporation  
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AS7C1024C
12/5/06, v. 1.0
Alliance Memory
P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
Read cycle (over the operating range)3,9
Parameter
Symbol
AS7C1024C-12
Unit
Notes
Min
Max
Read cycle time
tRC
12
–
ns
Address access time
tAA
–12
ns
3
Chip enable (CE1) access time
tACE1
–12
ns
3, 12
Chip enable (CE2) access time
tACE2
–12
ns
3, 12
Output enable (OE) access time
tOE
–6
ns
Output hold from address change
tOH
4–
ns
5
CE1 Low to output in low Z
tCLZ1
3
–
ns
4, 5, 12
CE2 High to output in low Z
tCLZ2
3
–
ns
4, 5, 12
CE1 Low to output in high Z
tCHZ1
0
6
ns
4, 5, 12
CE2 Low to output in high Z
tCHZ2
–
5
ns
4, 5, 12
OE Low to output in low Z
tOLZ
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
5
ns
4, 5
Power up time
tPU
0
–
ns
4, 5, 12
Power down time
tPD
–
12
ns
4, 5, 12
Undefined/don’t care
Falling input
Rising input
Address
DOUT
Data valid
tOH
tAA
tRC
supply
Current
CE2
OE
DOUT
tOE
tOLZ
tACE1, tACE2
tCHZ1, tCHZ2
tCLZ1, tCLZ2
tPU
tPD
ICC
ISB
50%
50%
Data valid
tRC1
CE1
tOHZ



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