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AS7C1024C 数据表(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C1024C 数据表(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 9 page ![]() September 2006 Advance Information Copyright © Alliance Memory All rights reserved. AS7C1024C 5V 128K X 8 CMOS SRAM 12/5/06, v. 1.0 Alliance Memory P. 1 of 9 ® Features • Industrial (-40o to 85oC) temperature • Organization: 131,072 x 8 bits • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages -300 mil SOJ -400 mil SOJ • ESD protection ≥ 2000 volts Logic block diagram Pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 131,702 x 8 Array (1,048,576) Input buffer I/O0 I/O7 OE CE1 WE Address decoder Control circuit A0 A1 A2 A3 A4 A5 A6 A7 VCC GND A8 CE2 |
类似零件编号 - AS7C1024C |
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类似说明 - AS7C1024C |
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