ADL5519ACPZ-R2 datasheet(36/39 Pages) AD

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ADL5519

Data Sheet

Rev. C | Page 36 of 39

EVALUATION BOARD

CONFIGURATION OPTIONS

Table 5. Evaluation Board (Rev. A) Configuration Options

Component

Description

Default Conditions

VPOS, VPSB, VPSR,

GND, GND1, GND3

Supply and Ground Connections.

VPOS, VPSB, and VPSR are internally connected.

GND, GND1, and GND3 are internally connected.

Not applicable

R0A, R0B, R5, R6,

R30, R31, C1, C2,

C3, C4

Input Interface.

The 52.3 Ω resistors in the R30 and R31 positions combine with the ADL5519

internal input impedance to give a broadband input impedance of about 50 Ω.

C1, C2, C3, and C4 are dc-blocking capacitors. A reactive impedance match can

be implemented by replacing R5, R6, R30, and R31 with an inductor and by

replacing C1, R0A and C4, R0B with appropriately valued capacitors.

R30, R31 = 52.3 Ω (Size 0402),

C1 to C4 = 47 nF (Size 0402)

R0A, R0B = 0 Ω

R5, R6 = open

R14

Temperature Sensor Interface.

Temperature sensor output voltage is available at the test point labeled TEMP.

R14 can be used as a pull-down resistor.

R14 = open (Size 0603)

R13, R17, R18,

R19, R27, R28,

R29

Temperature Compensation Interface.

A voltage source at ADJA, ADJB can be used to optimize the temperature

performance for various input frequencies. The pads for R27/R28 or R27/R29 can

be used for voltage dividers from the VREF node to set the ADJA, ADJB voltages

at different frequencies. The individual log channels can be disabled by installing

0 Ω resistors at R18 and R19.

R13, R17, R18, R19, R28, R29 = open

(Size 0603)

R27 = 0 Ω (Size 0603)

R8, R12, R15, R16,

R20, R21, R22,

R23, C13, C14

Output Interface, Measurement Mode.

In measurement mode, a portion of the output voltage is fed back to VSTA, VSTB via

R8, R12. The magnitude of the slope of the OUTA, OUTB output voltage response

can be increased by reducing the portion of VOUTA, VOUTB that is fed back to VSTA,

VSTB. The slope can be decreased by implementing a voltage divider by using

R20 and R16 or R21 and R15. R20 and R21 can also be used as a back-terminating

resistor or as part of a single-pole, low-pass filter.

R8, R12 = 0 Ω (Size 0603)

R15, R16, R22, R23 = open (Size 0603)

C13, C14 = open (Size 0603)

R20, R21 = 200 Ω (Size 0603)

R8, R12, R22, R23

Output Interface, Controller Mode.

In this mode, the 0 Ω resistors must be removed, leaving R8 and R12 open. In

controller mode, the ADL5519 can control the gain of an external component.

A setpoint voltage is applied to VSTA, VSTB, the value of which corresponds to

the desired RF input signal level applied to the corresponding ADL5519 RF input.

A sample of the RF output signal from this variable-gain component is selected,

typically via a directional coupler, and applied to ADL5519 RF input. The voltage

at OUTA, OUTB is applied to the gain control of the variable gain element. A control

voltage is applied to VSTA, VSTB. The magnitude of the control voltage can

optionally be attenuated via the voltage divider comprising R8, R12 and R22,

R23; or a capacitor can be installed in the R22, R23 position to form a low-pass

filter along with R8, R12.

R8, R12, R22, R23 = open (Size 0603)

R3, R4, R11, R24,

R25, R26, C7, C8,

C11, C12, C15, C16

Power Supply Decoupling.

The nominal supply decoupling consists of a 100 pF filter capacitor placed

physically close to the ADL5519 and a 0.1 μF capacitor placed nearer to each

power supply input pin.

R3, R4, R11, R24, R25, R26 = 0 Ω

(Size 0603)

C7, C8, C11 = 100 pF (Size 0603)

C12, C15, C16 = 0.1 μF (Size 0603)

R1, R2, R9, R10

Output Interface, Difference.

R9 and R10 can be replaced with a capacitor to form an integrator for constant

gain controller mode

R1, R2, R9, R10 = 0 Ω (Size 0603)

C9, C10

Filter Capacitor.

The low-pass corner frequency of the circuit that drives OUTA, OUTB can be

lowered by placing a capacitor between CLPA, CLPB and ground. Increasing this

capacitor increases the overall rise/fall time of the ADL5519 for pulsed input

signals. See the Output Filtering section for more details.

C9, C10 = 1000 pF (Size 0603)

R7, C6

VLVL Interface.

VREF can be used to drive VLVL through a voltage divider formed using R7 and C6.

R7 = open (Size 0603)

C6 = open (Size 0603)

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