TLC3544, TLC3548

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

17

POST OFFICE BOX 655303

detailed description (continued)

operation description

The converter samples the selected analog input signal, then converts the sample into digital output, according

to the selected output format. The converter has four digital input pins (SDI, SCLK, CS, and FS) and one digital

output pin (SDO) to communicate with the host device. SDI is a serial data input pin, SDO is a serial data output

pin, and SCLK is a serial clock from the host device. This clock is used to clock the serial data transfer. It can

also be used as the conversion clock source (see Table 2). CS and FS are used to start the operation. The

converter has a CSTART pin for an external hardware sampling and conversion trigger, and an INT/EOC pin

for interrupt purposes.

device initialization

After power on, the status of EOC/INT is initially high, and the input data register is set to all zeros. The device

must be initialized before starting the conversion. The initialization procedure depends on the working mode.

The first conversion result is ignored after power on.

Hardware Default Mode: Nonprogrammed Mode, Default. After power on, two consecutive active cycles

last 16 SCLKs at least. These cycles initialize the converter and load the CFR register with 800h (external

reference, unipolar straight binary output code, normal long sampling, internal OSC, single-ended input,

one-shot conversion mode, and EOC/INT pin as INT). No additional software configuration is required.

Software Programmed Mode: Programmed. When the converter has to be configured, the host must write

A000h into the converter first after power on, then perform the WRITE CFR operation to configure the device.

start of operation cycle

Each operation consists of several actions that the converter takes according to the command from the host.

The operation cycle includes three periods: command period, sampling period, and conversion period. In the

command period, the device decodes the command from the host. In the sampling period, the device samples

the selected analog signal according to the command. In the conversion period, the sample of the analog signal

is converted to digital format. The operation cycle starts from the command period, which is followed by one

or several sampling and conversion periods (depending on the setting) and finishes at the end of the last

conversion period.

The operation cycle is initiated by the falling edge of CS or the rising edge of FS.

CS Initiates The Operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation.

When CS is high, SDO is in the high-impedance state, the signals on SDI, and SDO are ignored, and SCLK is

disabled to clock the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI,

and SCLK. The MSB of the input data via SDI, ID[15], is latched at the first falling edge of SCLK following the

falling edge of CS. The MSB of output data from SDO, OD[15], is valid before this SCLK falling edge. This mode

works as an SPI interface when CS is used as the slave select (SS). It also can be used as a normal DSP

interface if CS connects to the frame sync output of the host DSP. FS must be tied high in this mode.

FS Initiates The Operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation,

resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. The ID[15] is latched at the first falling edge

of SCLK following the falling edge of FS. OD[15] is valid before this falling edge of SCLK. This mode is used

to interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame sync

of the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select to allow

the host DSP to access each device individually. If only one converter is used, CS can be tied low.

After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) are

shifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the output

data are valid before this falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to a

high-impedance state. The output data from SDO is the previous conversion result in one shot conversion

mode, or the contents in the top of the FIFO when the FIFO is used (refer to Figure 21).