TLC3544, TLC3548

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

20

POST OFFICE BOX 655303

sampling period (continued)

Normal Long Sampling Mode: This mode is the same as normal short sampling, except that it lasts 44 SCLK

periods.

Extended Sampling Mode: The external trigger signal, CSTART, triggers sampling and conversion. SCLK is

not used for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. The

falling edge of CSTART begins the sampling of the selected analog input. The sampling continues while

CSTART is low. The rising edge of CSTART ends the sampling and starts the conversion (with about 15 ns

internal delay). The occurrence of CSTART is independent of the SCLK clock, CS, and FS. However, the first

CSTART cannot occur before the rising edge of the 11th SCLK. In other words, the falling edge of the first

CSTART can happen at or after the rising edge of the 11th SCLK, but not before. The device enters the extended

sampling mode at the falling edge of CSTART and exits this mode once CSTART goes to high followed by two

consecutive falling edges of CS or two consecutive rising edges of FS (such as one read data operation followed

by a write CFR). The first CS or FS does not cause conversion. Extended mode is used when a fast SCLK is

not suitable for sampling, or when an extended sampling period is needed to accommodate different input signal

source impedance.

conversion period

The conversion period is the third portion of the operation cycle. It begins after the falling edge of the 16th SCLK

for normal short sampling mode, or after the falling edge of the 48th SCLK for normal long sampling, or on the

rising edge of CSTART (with 15 ns internal delay) for extended sampling mode.

The conversion takes 18 conversion clocks plus 15 ns. The conversion clock source can be an internal oscillator,

OSC, or an external clock, SCLK. The conversion clock is equal to the internal OSC if the internal clock is used,

or equal to SCLK/4 when the external clock is programmed. To avoid premature termination of the conversion,

enough time for the conversion must be allowed between consecutive triggers. EOC goes low at the beginning

of the conversion period and goes high at the end of the conversion period. INT goes low at the end of this period.

conversion mode

Four different conversion modes (mode 00, 01, 10, 11) are available. The operation of each mode is slightly

different, depending on how the converter samples and what host interface is used. Do not mix different types

of triggers throughout the repeat or sweep operations.

One Shot Mode (Mode 00): Each operation cycle performs one sampling and one conversion for the selected

channel. The FIFO is not used. When EOC is selected, it is generated while the conversion period is in progress.

Otherwise, INT is generated after the conversion is done. The result is output through the SDO pin during the

next select/conversion operation.

Repeat Mode (Mode 01): Each operation cycle performs multiple samplings and conversions for a fixed

channel selected according to the 4-bit command. The results are stored in the FIFO. The number of samples

to be taken is equal to the FIFO threshold programmed via D[1:0] in the CFR register. Once the threshold is

reached, INT is generated, and the operation ends. If the FIFO is not read after the conversions, the data are

replaced in the next operation. The operation of this mode starts with the WRITE CFR command to set

conversion mode 01, then the SELECT/CONVERSION command, followed by a number of samplings and

conversions of the fixed channel (triggered by CS, FS, or CSTART) until the FIFO threshold is hit. If CS or FS

triggers the sampling, the data on SDI must be any one of the SELECT CHANNEL commands. This data is a

dummy code for setting the converter in the conversion state. It does not change the existing channel selection

set at the start of the operation until the FIFO is full. After the operation finishes, the host can read the FIFO,

then reselect the channel and start the next REPEAT operation again; or immediately reselect the channel and

start the next REPEAT operation (by issuing CS, FS, or CSTAR), or reconfigure the converter and then start

a new operation according to the new setting. If CSTART triggers the sampling, the host can also immediately

start the next REPEAT (on the current channel) after the FIFO is full. Besides, if FS initiates the operation and

CSTART triggers the sampling and conversions, CS must not toggle during the conversion. This mode allows

the host to set up the converter, continue monitoring a fixed input, and to get a set of samples as needed.