Operating modes

M41T256Y

12/30

Figure 6.

Bus timing requirements sequence

Table 2.

AC characteristics

2.2

Read mode

In this mode the master reads the M41T256Y slave after setting the slave address (see

Figure 7 on page 13). Following the WRITE mode control bit (R/W=0) and the Acknowledge

Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of

address byte A(0) is a “Don’t care”). Next the START condition and slave address are

repeated followed by the READ mode control bit (R/W=1). At this point the master

transmitter becomes the master receiver. The data byte which was addressed will be

transmitted and the master receiver will send an acknowledge bit to the slave transmitter.

The address pointer is only incremented on reception of an acknowledge clock. The

M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the

Symbol

1.

Min

Max

Unit

SCL clock frequency

0

400

kHz

Time the bus must be free before a new transmission can

start

1.3

µs

SDA and SCL fall time

300

ns

Data hold time

0

µs

START condition hold time

(after this period the first clock pulse is generated)

600

ns

Clock high period

600

ns

Clock low period

1.3

µs

SDA and SCL rise time

300

ns

(2)

2.

Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL

Data setup time

100

ns

START condition setup time

(only relevant for a repeated start condition)

600

ns

STOP condition setup time

600

ns

AI00589

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P