M41T256Y

Clock operation

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3.5

Tamper indication circuit

The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used

to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable

bit (TEB) is set to a '1.'

This switch is normally open in the application, allowing the pin to be “floating” (internally

device has been physically moved or tampered with. The tamper bit is a “read only” bit and

is reset only by taking the tamper pin to ground and resetting the tamper enable bit to '0.'

This function operates both under normal power, and in battery back-up. If the switch closes

during a power-down condition, the bit will still be set correctly.

Note:

Upon initial battery attach or initial power application without the battery, the state of TEB

(and TB) will be undetermined. Therefore TEB must be initialized to a '0.'

3.6

Tamper event time-stamp

If a tamper occurs, not only will the tamper bit be set, but the event will also automatically be

time-stamped. This is accomplished by freezing the normal update of the clock registers

(7FF7h through 7FFFh) immediately following a tamper event. Thus, when tampering

occurs, the user may first read the time registers to determine exactly when the tamper

event occurred, then re-enable the clock update to the current time (and reset the Tamper

Bit, TB) by resetting the tamper enable bit (TEB).

The time update will then resume, and after either a stop condition or incrementing the

address pointer to a RAM address and back, the clock can be read to determine the current

time.

Note:

The tamper bit (TB) must always be set to '0' in order to read the current time.

3.7

Calibrating the clock

The M41T256Y is driven by a quartz controlled oscillator with a nominal frequency of

32,768Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator

calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at

25°C.

The oscillation rate of crystals changes with temperature (see Figure 11 on page 20).

Therefore, the M41T256Y design employs periodic counter correction. The calibration circuit

adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as

shown in Figure 12 on page 20. The number of times pulses which are blanked (subtracted,

negative calibration) or split (added, positive calibration) depends upon the value loaded into

the five calibration bits found in the control register. Adding counts speeds the clock up,

subtracting counts slows the clock down.

The calibration bits occupy the five lower order bits (D4-D0) in the control register (7FF8h).

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one