PCA9633DP2 datasheet(29/42 Pages) NXP

29 / 42 page

PCA9633_3

Product data sheet

Rev. 03 — 20 December 2006

29 of 42

NXP Semiconductors

PCA9633

4-bit Fm+ I2C-bus LED driver

[5]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undeﬁned region of SCL’s falling edge.

[6]

The maximum tf for the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time (tf) for the SDA output stage is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed tf.

[7]

Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Fig 23. Deﬁnition of timing

tSP

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Rise and fall times refer to VIL and VIH.

Fig 24. I2C-bus timing diagram

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tBUF

tSU;STA

tLOW

tHIGH

tVD;ACK

002aab285

tSU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 7

(D1)

bit 8

(D0)

1/fSCL

tVD;DAT

acknowledge

(A)

STOP

condition

(P)

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