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PCA9633DP2 数据表(PDF) 14 Page - NXP Semiconductors |
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PCA9633DP2 数据表(HTML) 14 Page - NXP Semiconductors |
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14 / 42 page ![]() PCA9633_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 20 December 2006 14 of 42 NXP Semiconductors PCA9633 4-bit Fm+ I2C-bus LED driver When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %). 7.3.5 Group frequency, GRPFREQ GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s). (in seconds) 7.3.6 LED driver output state, LEDOUT LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. duty cycle GDC 7:0 [] 256 --------------------------- = Table 12. GRPFREQ - Group Frequency register (address 07h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register global blinking period GFRQ 7:0 [] 1 + 24 ---------------------------------------- = Table 13. LEDOUT - LED driver output state register (address 08h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control 5:4 LDR2 R/W 00* LED2 output state control 3:2 LDR1 R/W 00* LED1 output state control 1:0 LDR0 R/W 00* LED0 output state control |
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