PCA9633_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 20 December 2006

13 of 42

NXP Semiconductors

PCA9633

[1]

See Section 7.7 “Using the PCA9633 with and without external drivers” for more details.

[2]

Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from

02h (PWM0) to 08h (LEDOUT) only.

[3]

See Section 7.4 “Active LOW output enable input” for more details.

[4]

OUTNE[1:0] is only for PCA9633 16-pin version.

7.3.3 PWM registers 0 to 3, PWMx—Individual brightness control registers

A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through

256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT register).

7.3.4 Group duty cycle control, GRPPWM

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency

signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is

then used as a global brightness control allowing the LED outputs to be dimmed with the

same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 4 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

1 to 0

OUTNE[1:0]

[3][4]

R/W

00

When OE = 1 (output drivers not enabled), LEDn = 0.

01*

When OE = 1 (output drivers not enabled):

LEDn = 1 when OUTDRV = 1

LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)

10

When OE = 1 (output drivers not enabled), LEDn = high-impedance.

11

reserved

Table 9.

Legend: * default value.

Bit

Symbol

Access

Value

Description

Table 10.

PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description

Legend: * default value.

Address

Register

Bit

Symbol

Access

Value

Description

02h

PWM0

7:0

IDC0[7:0]

R/W

0000 0000* PWM0 Individual Duty Cycle

03h

PWM1

7:0

IDC1[7:0]

R/W

0000 0000* PWM1 Individual Duty Cycle

04h

PWM2

7:0

IDC2[7:0]

R/W

0000 0000* PWM2 Individual Duty Cycle

05h

PWM3

7:0

IDC3[7:0]

R/W

0000 0000* PWM3 Individual Duty Cycle

duty cycle

IDC 7:0

[]

256

------------------------

=

Table 11.

GRPPWM - Group duty cycle control register (address 06h) bit description

Legend: * default value.

Address

Register

Bit

Symbol

Access

Value

Description

06h

GRPPWM

7:0

GDC[7:0]

R/W

1111 1111

GRPPWM register