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TMP86CS64AFG 数据表(PDF) 49 Page - Toshiba Semiconductor |
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TMP86CS64AFG 数据表(HTML) 49 Page - Toshiba Semiconductor |
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49 / 202 page  Page 39 TMP86CS64AFG 3. Interrupt Control Circuit The TMP86CS64AFG has a total of 21 interrupt sources excluding reset, of which 5 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter- rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi- nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inter- rupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is cancelled). For details, see “Address Trap”. Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer". 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter- rupt. All interrupt latches are initialized to “0” during reset. Interrupt Factors Enable Condition Interrupt Latch Vector Address Priority Internal/External (Reset) Non-maskable – FFFE 1 Internal INTSWI (Software interrupt) Non-maskable – FFFC 2 Internal INTUNDEF (Executed the undefined instruction interrupt) Non-maskable – FFFC 2 Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2 Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2 External INT0 IMF• EF4 = 1, INT0EN = 1 IL4 FFF6 5 External INT1 IMF• EF5 = 1 IL5 FFF4 6 Internal INTTC4 IMF• EF6 = 1 IL6 FFF2 7 Internal INTTC5 IMF• EF7 = 1 IL7 FFF0 8 Internal INTTBT IMF• EF8 = 1, IL8ER = 0 IL8 FFEE 9 External INT2 IMF• EF8 = 1, IL8ER = 1 Internal INTTC1 IMF• EF9 = 1, IL9ER = 0 IL9 FFEC 10 External INT3 IMF• EF9 = 1, IL9ER = 1 Internal INTTC3 IMF• EF10 = 1 IL10 FFEA 11 Internal INTTC6 IMF• EF11 = 1 IL11 FFE8 12 Internal INTTC2 IMF• EF12 = 1 IL12 FFE6 13 Internal INTSIO1 IMF• EF13 = 1, IL13ER = 0 IL13 FFE4 14 External INT4 IMF• EF13 = 1, IL13ER = 1 Internal INTTRX IMF• EF14 = 1, IL14ER = 0 IL14 FFE2 15 External INT5 IMF• EF14 = 1, IL14ER = 1 Internal INTADC IMF• EF15 = 1, IL15ER = 0 IL15 FFE0 16 Internal INTSIO2 IMF• EF15 = 1, IL15ER = 1 |
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