TMP86CS64AFG datasheet(21/202 Pages) TOSHIBA

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Page 11

TMP86CS64AFG

2. Operational Descriptions

2.1 CPU Core Function

The CPU core consists of a CPU, a system clock controller and an interrupt controller.

This chapter provides descriptions of the CPU core, the program memory, the data memory and the reset circuit.

2.1.1 Memory Address Map

TMP86CS64AFG memory consists of RAM and Special Function Register (SFR), which are mapped to a

64 Kbyte address space.

The TMP86CS64AFG memory consists of MaskROM, RAM, Special Function Register (SFR) and Data

Buffer Resister (DBR), which are mapped to a 64 kbyte address space.

Figure 2-1 shows the TMP86CS64AFG memory address map.

Figure 2-1 Memory Address Map

SFR

0000H

64 bytes

SFR:

RAM:

Special function register

I/O port

Peripheral hardware control register

Peripheral hardware status register

System control register

Program status word

Random access memory

Data memory

Stack

003FH

RAM

0040H

2048

bytes

083FH

DBR

0F80H

128

bytes

DBR:

Data buffer register

Peripheral hardware control register

Peripheral hardware status register

0FFFH

1000H

MaskROM:

Program memory

MaskROM

61440

bytes

FFC0H

Vector table for vector call instructions

(32 bytes)

FFDFH

FFE0H

Instruction vector table

(32 bytes)

FFFFH

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